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Low-Power CMOS Random Access Memory Circuits

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Book cover Low-Power Digital VLSI Design

Abstract

Low-power Random Access Memory (RAM) has seen a remarkable and rapid progress in power reduction. Many circuits techniques for active and standby power reduction in static and dynamic RAMs have been devised. In this chapter we study low-power memory circuit techniques which are very interesting for several other applications. Among these circuits, we examine memory cells, sense amplifiers, precharging circuits, etc. Circuit techniques for 1.x V power supply are also discussed. The voltage targets using NiCd and Mn batteries are 1.2 and 1.5 V respectively. The minimum voltage of a NiCd cell is 0.9 V. Also we consider the Voltage Down Converters (VDCs) which are used in memories and processors. No consideration is given to the detail of designing a complete memory chip because a single configuration requires an entire book.

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References

  1. H. Tran et al., “An 8-ns 1-Mb ECL BiCMOS SRAM with a Configurable Memory Array Size,” International Solid-State Circuits Conf. Tech. Dig., pp. 36–37, February 1989.

    Google Scholar 

  2. M. Matsui et al., “An 8-ns 1-Mb ECL BiCMOS SRAM,” International Solid-State Circuits Conf. Tech. Dig., pp. 38–39, February 1989.

    Google Scholar 

  3. Y. Maki et al., “A 6.5-ns 1 Mb BiCMOS ECL SRAM,” International Solid-State Circuits Conf. Tech. Dig., pp. 136–137, February 1990.

    Google Scholar 

  4. M. Takada et al., “A 5-ns 1-Mb ECL BiCMOS SRAM,” IEEE Journal of Solid State Circuits, vol. 25, no. 5, pp. 1057–1062, October 1990.

    Article  MathSciNet  Google Scholar 

  5. A. Ohba et al., “A 7-ns 1-Mb BiCMOS ECL SRAM with Program-Free Redundancy,” in Symp. VLSI Circuits Conf. Tech. Dig., pp. 41–42, May 1990.

    Google Scholar 

  6. Y. Okajima et al., “A 7-ns 4-Mb BiCMOS SRAM with a ParaUel Testing Circuit,” International Solid-State Circuits Conf. Tech. Dig., pp. 54–55, February 1991.

    Google Scholar 

  7. K. Sasaki et al., “A 7-ns 140-mW 1-Mb CMOS SRAM with Current Sense Amplifier,” IEEE Journal of Solid-State Circuits, vol. 27, no. 11, pp. 1511–1518, November 1992.

    Article  Google Scholar 

  8. T. Ootani et al., “A 4-Mb CMOS SRAM with a PMOS Thin-Film Transistor Load Cell,” IEEE Journal of Solid-State Circuits, vol. 25, no. 5, pp. 1082–1092, October 1990.

    Article  Google Scholar 

  9. S. Murakami et al., “A 21-mW 4-Mb CMOS SRAM for Battery Operation,” IEEE Journal of Solid-State Circuits, vol. 26, no. 11, pp. 1563–1570, November 1991.

    Article  MathSciNet  Google Scholar 

  10. K. Sasaki et al., “16-Mb CMOS SRAM with 1 2.3-µm2 Single-Bit-Line Memory Cell,” IEEE Journal of Solid-State Circuits, vol. 28, no. 11, pp. 1125–1130, November 1993.

    Article  Google Scholar 

  11. M. Matsumiya et al., “A 15-ns 16-Mb CMOS SRAM with Interdigitated Bit-Line Architecture,” IEEE Journal of Solid-State Circuits, vol. 27, no. 11, pp. 1497–1503, November 1992.

    Article  Google Scholar 

  12. K. Seno et al., “A 9-ns 16-Mb CMOS SRAM with Offset-Compensated Current Sense Amplifier,” IEEE Journal of Solid-State Circuits, vol. 28, no. 11, pp. 1119–1124, November 1993.

    Article  Google Scholar 

  13. E. Seevinck, F. J. List, and J. Lohstroh, “ Static-Noise Margin Analysis of MOS SRAM Cells,” IEEE Journal of Solid-State Circuits, vol. SC-22, no. 5, pp. 748–754, October 1987.

    Article  Google Scholar 

  14. H. Kato et al., “Consideration of Poly-Si Loaded Cell Capacity Limits for Low-Power and High-Speed,” IEEE Journal of Solid-State Circuits, vol. 27, no. 4, pp. 683–685, April 1992.

    Article  Google Scholar 

  15. K. Sasaki et al., “A 23-ns 4-Mb CMOS SRAM with 0.2-µA Standby Current,” IEEE Journal of Solid-State Circuits, vol. 25, no. 5, pp. 1075–1081, October 1990.

    Article  Google Scholar 

  16. K. Ishibashi, T. Yamanaka, and K. Shimohigashi, “An α-Immune, 2-V Supply Voltage SRAM using a Polysilicon PMOS Load Cell,” IEEE Journal of Solid-State Circuits, vol. 25, no. 1, pp. 55–60, February 1990.

    Article  Google Scholar 

  17. K. Sasaki et al., “A 15-ns 1-Mbit CMOS SRAM,” IEEE Journal of Solid-State Circuits, vol. 23, no. 5, pp. 1067–1072, October 1988.

    Article  Google Scholar 

  18. K. Sasaki et al., “A 9-ns 1-Mbit CMOS SRAM,” IEEE Journal of Solid-State Circuits, vol. 24, no. 5, pp. 1219–1225, October 1989.

    Article  Google Scholar 

  19. K. Ishibashi, K. Takasugi, T. Yamanaka, T. Hashimoto, K. Sasaki, “ A 1-V TFT-Load SRAM using a Two-Step Word-Voltage Method,” IEEE Journal of Solid-State Circuits, vol. 27, no. 11, pp. 1519–1524, May 1992.

    Article  Google Scholar 

  20. M. Yoshimito, K. Anami, H. Shinohara, T. Yoshihara, H. Takagi, S. Nagao, S. Kayano, and T. Nakano, “A Divided Word-Line Structure in the Static RAM and its Application to a 64K Full CMOS RAM,” IEEE Journal of Solid-State Circuits, vol. SC-18, no. 5, pp. 479–485, October 1983.

    Article  Google Scholar 

  21. T. Hirose, H. Kuriyama, S. Murakami, K. Yuzuriha, T. Mukai, K. Tsut-sumi, Y. Nishimura, Y. Kohno, and K. Anami, “A 20-ns 4-Mb CMOS SRAM with Hierarchical Word Decoding Architecture,” IEEE Journal of Solid-State Circuits, vol. 25, no. 5, pp. 1068–1074, October 1990.

    Article  Google Scholar 

  22. A. Sekiyama, T. Seki, S. Nagai, A. Iwase, N. Suziki, and M. Hayasaka, “A 1-V Operating 256-Kb Full-CMOS SRAM,” IEEE Journal of Solid-State Circuits, vol. 27, no. 5, pp. 776–782, May 1992.

    Article  Google Scholar 

  23. T. Yabe, et al., “High-Speed and Low-Standby-Power Circuit Design of 1 to 5 V Operating 1 Mb Full CMOS SRAM,” Symposium on VLSI Circuits Tech. Dig., pp. 107–108, May 1993.

    Google Scholar 

  24. G. Kitsukawa, et al., “256-Mb DRAM Circuit Technologies for File Applications,” IEEE Journal of Solid-State Circuits, vol. 28, no. 11, pp. 1105–1113, November 1993.

    Article  Google Scholar 

  25. T. Hasegawa, et al., “An Experimental DRAM with a NAND-Structured Cell,” IEEE Journal of Solid-State Circuits, vol. 28, no. 11, pp. 1099–1104, November 1993.

    Article  Google Scholar 

  26. T. Sugibayashi, et al., “A 30-ns 256-Mb DRAM with a Multidivided Array Structure,” IEEE Journal of Solid-State Circuits, vol. 28, no. 11, pp. 1092–1099, November 1993.

    Article  Google Scholar 

  27. M. Aoki, J. Etoh, K. Itoh, S-I. Kimura, and Y. Kawamoto, “A 1.5-VDRAM for Battery-Based Applications,” IEEE Journal of Solid-State Circuits, vol. 24, no. 5, pp. 1206–1212, October 1989.

    Article  Google Scholar 

  28. Y. Nakagome, et al., “An Experimental 1.5-V 64-Mb DRAM,” IEEE Journal of Solid-State Circuits, vol. 26, no. 4, pp. 465–471, April 1991.

    Article  Google Scholar 

  29. H. Yamauchi, et al., “A Circuit Technology for High-Speed Battery-Operated 16-Mb CMOS DRAMs,” IEEE Journal of Solid-State Circuits, vol. 28, no. 11, pp. 1084–1091, November 1993.

    Article  Google Scholar 

  30. N. C. C. Lu, “ Advanced Cell Structures for Dynamic RAMs,” IEEE Circuits and Devices Magazine, no. 1, pp. 27–36, January 1989.

    Google Scholar 

  31. M. Takada, “DRAM Technology for Giga-bit Age,” International Conf. Solid State Devices and Materials, Tech. Dig., pp. 874–876, 1993.

    Google Scholar 

  32. L. Itoh, et al., “An Experimental 1-Mb DRAM with on Chip Voltage Limiter,” in International Solid-State Circuits Conf., Tech. Dig., pp. 282–283, 1984.

    Google Scholar 

  33. N. C-C. Lu, and H. H. Chao, “ Half-Vdd Bit-Line Sensing Scheme in CMOS DRAMs,” IEEE Journal of Solid-State Circuits, vol. SC-19, no. 5, pp. 451–454, August 1984.

    Article  Google Scholar 

  34. H. Kawamoto, T. Shinoda, Y. Yamaguchi, S. Shimizu, K. Ohishi, N. Tan-imura, T. Yasui, “A 288K CMOS Pseudostatic RAM,” IEEE Journal of Solid-State Circuits, vol. SC-19, no. 5, pp. 619–623, October 1984.

    Article  Google Scholar 

  35. Y. Tsikikawa et al., “An Efficient Back-Bias Generator with Hybrid Pumping Circuit for 1.5 V DRAMs,” in Symposium of VLSI Circuits, Tech. Dig., pp. 85–86, May 1993.

    Google Scholar 

  36. Y. Konishi, et al., “A 38-ns 4-Mb DRAM with a Battery-Backup (BBU) Mode,” IEEE Journal of Solid-State Circuits, vol. 25, no. 5, pp. 1112–1117, October 1990.

    Article  Google Scholar 

  37. T. Ooishi, et al., “A Well-Synchronized Sensing/Equalizing Method for Sub-1 V Operating Advanced DRAMs,” in Symposium on VLSI Circuits, Tech. Dig., pp. 81–82, May 1993.

    Google Scholar 

  38. M. Asakura, et al., “An Experimental 256-Mb DRAM with Boosted Sense-Ground Scheme,” IEEE Journal of Solid-State Circuits, vol. 29, no. 11, pp. 1303–1309, November 1994.

    Article  Google Scholar 

  39. T. Sakata et al., “Subthreshold-Current Reduction Circuits for Multi-Gigabit DRAMs,” in Symposium on VLSI Circuits, Tech. Dig., pp. 45–46, May 1993.

    Google Scholar 

  40. T. Furuyama, et al., “A New On-Chip Voltage Converter for Submicrometer High-Density DRAMs,” IEEE Journal of Solid-State Circuits, vol. 22, no. 3, pp. 437–441, June 1987.

    Article  Google Scholar 

  41. M. Takada, et al., “A 4-Mb DRAM with Half Internal Voltage Bit-Line Precharge,” IEEE Journal of Solid-State Circuits, vol. 21, no. 5, pp. 612–617, October 1986.

    Article  Google Scholar 

  42. M. Hiroguchi, et al., “Dual-Operation-Voltage Scheme for a Single 5-V, 16-Mb DRAM,” IEEE Journal of Solid-State Circuits, vol. 23, no. 5, pp. 1128–1132, October 1988.

    Article  Google Scholar 

  43. G. Kitsukawa, et al., “A 1-Mb BiCMOS DRAM using Temperature-Compensation Circuit Techniques,” IEEE Journal of Solid-State Circuits, vol. 24, no. 3, pp. 597–602, June 1989.

    Article  Google Scholar 

  44. M. Horiguchi, et al., “A Tunable CMOS-DRAM Voltage Limiter with Stabilized Feedback Amplifier,” IEEE Journal of Solid-State Circuits, vol. 25, no. 5, pp. 1129–1135, October 1990.

    Article  MathSciNet  Google Scholar 

  45. M. Horiguchi, et al., “Dual-Regulator Dual-Decoding-Trimmer DRAM Voltage Limiter for Burn-in Test,” IEEE Journal of Solid-State Circuits, vol. 26, no. 11, pp. 1544–1549, November 1991.

    Article  Google Scholar 

  46. K. Ishibashi, K. Sasaki, and H. Toyoshima, “ A Voltage Down Converter with Submicroampere Standby Current for Low-Power Static RAMs,” IEEE Journal of Solid-State Circuits, vol. 27, no. 6, pp. 920–926, June 1992.

    Article  Google Scholar 

  47. P. E. Allen, and D. R. Holberg, “CMOS Analog Circuit Design,” Holt, Rinehart and Winston Publisher, 1987.

    Google Scholar 

  48. P. R. Gray, and R. G. Meyer, “Analysis and Design of Analog Integrated Circuit,”2nd Edition Wiley Publisher, 1984.

    Google Scholar 

  49. R. A. Blauschild et al., “A New NMOS Temperature Stable Voltage Reference,” IEEE Journal of Solid-State Circuits, vol. SC-13, pp. 767–774, December 1978.

    Article  Google Scholar 

  50. H. Tanaka, Y. Nakagome, J. Etoh, E. Yamasaki, M. Aoki, and K. Miyazawa, “Sub-l-µm Dynamic Reference Voltage Generator for Battery-Operated DRAMs,” in Symp. VLSI Circuits, Tech. Dig., pp. 87–88, May 1993.

    Google Scholar 

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Authors and Affiliations

  1. University of Waterloo, Canada

    Abdellatif Bellaouar & Mohamed I. Elmasry

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  1. Abdellatif Bellaouar
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  2. Mohamed I. Elmasry
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© 1995 Springer Science+Business Media New York

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Bellaouar, A., Elmasry, M.I. (1995). Low-Power CMOS Random Access Memory Circuits. In: Low-Power Digital VLSI Design. Springer, Boston, MA. https://doi.org/10.1007/978-1-4615-2355-0_6

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  • DOI: https://doi.org/10.1007/978-1-4615-2355-0_6

  • Publisher Name: Springer, Boston, MA

  • Print ISBN: 978-1-4613-5999-9

  • Online ISBN: 978-1-4615-2355-0

  • eBook Packages: Springer Book Archive

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