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Low-Voltage VLSI BiCMOS Circuit Design

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Book cover Low-Power Digital VLSI Design

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Abstract

BiCMOS technology offers enhanced performance compared to CMOS at 5 V power supply voltage. Many high-speed BiCMOS SRAMs, gate arrays, ASICs, etc. have been fabricated [1]. In this chapter, we present a variety of BiCMOS logic circuits suitable for 3.3 and sub-3.3 V. The potential gates for digital applications are identified. The chapter starts with the introduction of the conventional BiCMOS (totem-pole) gate which is used in 5 V applications. The degradation of this gate, with supply voltage scaling, is demonstrated. In Section 5.2, we introduce the BiNMOS family suitable for low-voltage applications. Other logic families, for low power supply voltage operation, are discussed in Section 5.3. Low-voltage digital applications of BiCMOS are identified. The reader is referred to BiCMOS books [2, 3] to get more familiar with BiCMOS circuits.

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Authors and Affiliations

  1. University of Waterloo, Canada

    Abdellatif Bellaouar & Mohamed I. Elmasry

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  1. Abdellatif Bellaouar
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  2. Mohamed I. Elmasry
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© 1995 Springer Science+Business Media New York

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Bellaouar, A., Elmasry, M.I. (1995). Low-Voltage VLSI BiCMOS Circuit Design. In: Low-Power Digital VLSI Design. Springer, Boston, MA. https://doi.org/10.1007/978-1-4615-2355-0_5

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  • DOI: https://doi.org/10.1007/978-1-4615-2355-0_5

  • Publisher Name: Springer, Boston, MA

  • Print ISBN: 978-1-4613-5999-9

  • Online ISBN: 978-1-4615-2355-0

  • eBook Packages: Springer Book Archive

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