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Low-Voltage Low-Power VLSI CMOS Circuit Design

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Low-Power Digital VLSI Design

Abstract

In this chapter we introduce the CMOS logic gate with the development of simple models for delay and power dissipation estimation. These analysis permit us to understand the mechanisms that control the performance, particularly the power dissipation, of a logic circuit. Several CMOS design styles, such as pseudo-NMOS, dynamic logic and NORA, are presented. Other circuit variations of the static complementary CMOS, which are suitable for low-power applications, are discussed. These include the pass-transistor logic families such as Complementary Pass-transistor Logic (CPL), Dual Pass-transistor Logic (DPL), and Swing Restored Pass-transistor Logic (SRPL). Also an overview of clocking strategy in VLSI systems is covered. Included in this chapter is one important area which is the I/O circuits. The power dissipation of the I/O circuits is also analyzed. Finally, low-power techniques for CMOS design are also reviewed at the transistor-level. We will cover the low-power issues at subsystem/system/architecture levels in Chapter 6, 7 and 8 in more detail. Several books treat in detail other CMOS circuit design aspects [1, 2, 3]. The reader can refer to them.

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Authors and Affiliations

  1. University of Waterloo, Canada

    Abdellatif Bellaouar & Mohamed I. Elmasry

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  1. Abdellatif Bellaouar
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  2. Mohamed I. Elmasry
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© 1995 Springer Science+Business Media New York

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Bellaouar, A., Elmasry, M.I. (1995). Low-Voltage Low-Power VLSI CMOS Circuit Design. In: Low-Power Digital VLSI Design. Springer, Boston, MA. https://doi.org/10.1007/978-1-4615-2355-0_4

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  • DOI: https://doi.org/10.1007/978-1-4615-2355-0_4

  • Publisher Name: Springer, Boston, MA

  • Print ISBN: 978-1-4613-5999-9

  • Online ISBN: 978-1-4615-2355-0

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