Abstract
Historically, VLSI designers have used circuit speed as the “performance” metric. Large gains, in terms of performance and silicon area, have been made for digital processors, microprocessors, DSPs (Digital Signal Processors), ASICs (Application Specific ICs), etc. In general, “small area” and “high performance” are two conflicting constraints. The IC designers’ activities have been involved in trading off these constraints. Power dissipation issue was not a design criterion but an afterthought. In fact, power considerations have been the ultimate design criteria in special portable applications such as wristwatches and pacemakers for a long time. The objective in these applications was minimum power for maximum battery life time.
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References
Special Report, “The New Contenders,” IEEE Spectrum, pp. 20–25, December 1993.
D. W. Dobberpuhl et al., “A 200-MHz 64-b Dual-Issue CMOS Microprocessor”, IEEE J. Solid-State Circuits, vol. 27, no. 11, pp. 1555–1567, November 1992.
W. J. Bowhill et al., “A 300MHz 64b Quad-Issue CMOS RISC Microprocessor,” IEEE International Solid-State Circuits Conf., Tech. Dig., pp. 182–183, February 1995.
Technology 1995: Solid State, IEEE Spectrum, pp. 35–39, January 1995.
D. Bearden, et al., “A 133 MHz 64b Four-Issue CMOS Microprocessor,” IEEE International Solid-State Circuits Conf., Tech. Dig., pp. 174–175, February 1995.
MIPS Press release, 1994.
A. Charnas, et al., “A 64b Microprocessor with Multimedia Support,” IEEE International Solid-State Circuits Conf., Tech. Dig., pp. 178–179, February 1995.
C. Small, “Shrinking Devices Put the Squeeze on System Packaging,” EDN, vol. 39, no. 4, pp. 41–46, February 1994.
P. Verhofstadt, “Keynote Address,” IEEE Symposium on Low Power Electronics, Tech. Dig., October 1994.
G. Gerosa, et al., “A 2.2 W 80 MHz Superscalar RISC Microprocessor,” EEE Journal of Solid-State Circuits, vol. 29, no. 12, pp. 1440–1454, December 1994.
R. Bechade, et al., “A 32b 66MHz Microprocessor,” IEEE International Solid-State Circuits Conference, Tech. Dig., pp. 208–209, February 1994.
N. K. Yeung, Y-H. Sutu, T. Y-F. Su, E. T. pak, C-C Chao, S. Akki, D. D. Yau, and R. Lodenquai, “The Design of a 55SPECint92 RISC Processor under 2W,” IEEE International Solid-State Circuits Conference, Tech. Dig., pp. 206–207, February 1994.
S. Lipoff and A. D. Little, “Evaluation of New Battery Technology in Selected Applications,” IEEE Workshop on Low-power Electronics, Phoenix, AZ, August 1993.
J. M. C. Stork, “Technology Leverage for Ultra-Low Power Information Systems,” IEEE Symposium on Low Power Electronics, Tech. Dig., pp. 52–55, October 1994.
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© 1995 Springer Science+Business Media New York
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Bellaouar, A., Elmasry, M.I. (1995). Low-Power VLSI Design: An Overview. In: Low-Power Digital VLSI Design. Springer, Boston, MA. https://doi.org/10.1007/978-1-4615-2355-0_1
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DOI: https://doi.org/10.1007/978-1-4615-2355-0_1
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