Over-the-Cell Routing and Via Minimization

Abstract

The current trend in VLSI design is to develop high performance chips. The main objective of physical design is satisfy the performance needs while mini-mizing the die size. Historically, the gate delays limited the chip performance. The developments in fabrication process technology in the past two decades have resulted in a phenomenal decrease in feature sizes, and introduced addi-tional metal layers for interconnections(routing). Sub-micron processes with five to seven metal layers for interconnections are now available for design of high performance and high density chips. The number of devices in a chip have increased from about a thousand devices in the early 70’s to over tens of million devices now. The increase in the number of devices has led to a significant increase in number of interconnections. Interconnect delays, which were considered to be insignificant earlier, have now become comparable, if not more prominent than the gate delays.