Minimizing Switched Capacitance

  • Anantha P. Chandrakasan
  • Robert W. Brodersen


In the previous chapter, power dissipation was minimized in CMOS circuits by aggressive supply voltage scaling. Since CMOS circuits do not dissipate power if they are not switching, another approach to low power design is to reduce the switching activity to the minimal level required to perform the computation. This can range from simply powering down the complete circuit or portions of it, to more sophisticated schemes in which the clocks are gated or optimized circuit architectures are used which minimize the number of transitions. The focus of this chapter is on minimizing the switched capacitance at all levels of the design. The following sections describe a system level approach to minimize the switched capacitance which involves optimizing algorithms, architectures, logic design, circuit design, and physical design.


Vector Quantization Switching Activity Dynamic Logic Gray Code Data Word 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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Copyright information

© Springer Science+Business Media New York 1995

Authors and Affiliations

  • Anantha P. Chandrakasan
    • 1
  • Robert W. Brodersen
    • 2
  1. 1.Massachusetts Institute of TechnologyUSA
  2. 2.University of California/BerkeleyUSA

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