Retargetable Code Generation for Parallel, Pipelined Processor Structures
The demand for decreased turn around time in the design of programmable digital circuits requires CAD tools for synthesis, verification and code generation. Usually a RT level netlist is available as soon as the datapath is designed. Given the netlist and the behavior of the RT level modules, the proposed compiler maps a source program to the binary code of the target machine.
The main tasks of the compiler are allocation, register allocation, scheduling and compaction. These tasks are highly interdependent. Some machine features such as operator chaining, multi-cycle operations, pipeline latency, load delay, delayed branch, or residual control give rise to instruction dependencies, which can be automatically extracted from the structural description.
From the netlist the proposed compiler derives an internal target machine representation, that is general enough to support all target architecture features mentioned above.
In case the hardware supports different operators for a given operation the code generator must not commit to one of them, until a suitable alternative can be determined. In order to generate high quality code and to support irregular architectures, the code generator examines the alternative code versions.
KeywordsAssure Compaction Alloca
Unable to display preview. Download preview PDF.