Abstract
Macromodeling for timing simulation consists of two important parts: analysis of the primitive macromodel and reduction of complex gates to that macromodel. This chapter primarily addresses the first part and concentrates on the second part. In this chapter, a nonlinear macromodel for estimating performance of CMOS gates is presented which applies more detailed device modeling than other fast-timing techniques.
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© 1995 Springer Science+Business Media New York
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Kong, JT., Overhauser, D. (1995). A Nonlinear Macromodel. In: Digital Timing Macromodeling for VLSI Design Verification. The Springer International Series in Engineering and Computer Science, vol 319. Springer, Boston, MA. https://doi.org/10.1007/978-1-4615-2321-5_3
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DOI: https://doi.org/10.1007/978-1-4615-2321-5_3
Publisher Name: Springer, Boston, MA
Print ISBN: 978-1-4613-5982-1
Online ISBN: 978-1-4615-2321-5
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