Abstract
With energy-recovery CMOS, circuit energy that would otherwise be dissipated as heat is instead conserved for later reuse. From such an approach to low power, there are no a priori limits to the degree to which energy and power dissipation can be reduced inside a circuit. By externally controlling the length and shape of the signal transitions, the energy expended to transition a signal between logic levels can be reduced to an arbitrarily small degree. In contrast, unconventional digital CMOS circuits, the energy dissipated to “flip a bit” from one to zero or vice versa is a fixed and non-negotiable quantity on the order of (1/2) CV 2 Methods and techniques to reduce dissipation are thus limited to minimizing the number of transitions required to carry out a computation, or reducing the magnitude of the individual capacitances (C) or the voltage swing (V) between logic levels zero and one. These methods offer significant energy and power reduction but they are ultimately limited by (1/2) CV 2.
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Athas, W.C. (1996). Energy-Recovery CMOS. In: Rabaey, J.M., Pedram, M. (eds) Low Power Design Methodologies. The Springer International Series in Engineering and Computer Science, vol 336. Springer, Boston, MA. https://doi.org/10.1007/978-1-4615-2307-9_4
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DOI: https://doi.org/10.1007/978-1-4615-2307-9_4
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