Design and performance Evaluation of a Fault-Tolerant, Hard-Real-Time, Parallel Processor

  • Robert Clasen
  • Rick Harper
  • Edward Czeck
Part of the The Springer International Series in Engineering and Computer Science book series (SECS, volume 297)


The continuing integration of computer systems into critical control applications requires that the systems tolerate any hardware fault which may occur during operations. Additionally, the control stability aspects of these applications require that data operations (such as input, processing, and output) be performed within some bounded real-time constraints. Any missed time deadlines can be viewed as system failures, with results as consequential as hardware failures. Thus contemporary designs must consider both the hardware fault tolerance as well as the deterministic scheduling of real-time tasks.


Rate Group Network Element Hardware Fault Iteration Rate Minor Frame 
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Copyright information

© Springer Science+Business Media New York 1995

Authors and Affiliations

  • Robert Clasen
    • 1
  • Rick Harper
    • 1
  • Edward Czeck
    • 2
  1. 1.Advanced Computer Architectures GroupThe Charles Stark Draper LaboratoryCambridge
  2. 2.Electrical and Computer Engineering Department409 Dana Research Building, Northeastern UniversityBoston

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