Abstract
The concept for the ADENA (Alternating Direction Edition Nexus Array) computer was created in the late 1970s by Nogi [1, 2, 3, 4, 5]. In those days, the demands of supercomputing began to grow in science and technology, and only the vector processor was widely accepted as a supercomputer, while the ILLIAC-IV, an early parallel computer, was already destined to retire. Nogi had a perspective that the vector processor might be replaced or strengthened by parallel processing facilities in the next generation, and thought that it would be very important to get a new, more sophisticated parallel machine based upon some new ideas specifically dedicated to number-crunching scientific computation. Seeing the decline of the ILLIAC-IV, he considered that a parallel computer should not be based only upon the computational style of any explicit schemes for PDEs(Partial Differential Equations), as firstly imagined by L. F. Richardson, a famous meteorologist, and later by adherents to his idea, including the developers of the ILLIAC-IV. Nogi considered that it might be better to avoid any grid architecture of processors. We already had some excellent implicit schemes that were clearly more efficient than any explicit ones on conventional machines and were hence becoming accepted for many complex application problems, even though these implicit schemes were considered, at first glance, inefficient for parallel processing.
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References
T. Nogi and M. Kubo, “ADINA Computer LI. Architecture and Theoretical Estimates, ” Mem. Fac. Eng. Kyoto Univ, 42(4):421–439, 1980.
T. Nogi, “ADINA Computer II. I. Architecture and Theoretical Estimates, ” Mem. Fac. Eng. Kyoto Univ., 43(1):124–144, 1981.
T. Nogi, “ADINA Computer I and II. II. Data Structure, ” Mem. Fac.Eng. Kyoto Univ., 43(3):434–450, 1981.
T. Nogi, “Parallel Machine ADINA, ” R. Glowinsky and J.L. Lons (eds.), Computing Methods in Applied Science and Engineering V, pages 103-122, Amsterdam, North-Holland, 1982.
T. Nogi, “Parallel Computation, ” Pattern and Waves, Studies in Mathematics and its Applications 18, pages 279–318. Kinokuniya/North-Holland, 1986.
H. Kadota, K. Kaneko, Y. Tanikawa, and T. Nogi, “VLSI Parallel Computer with Data Transfer Network: ADENA, ” Proc. 1989 International Conference on Parallel Processing, pages 1319–322,1990.
A. Wakatani et al., “The Implementation of a Parallel Programming Language: ADETRAN, ” IPSJ Technical report 90-5F-37, pages 1–10, December 1990 (in Japanese).
S. Sasaki et al., “Programming Environment of the ADENA System, ” The 40th Annual Convention IPS Japan, pages 1243–1244, 1990 (in Japanese).
K. Zaiki et al., “APARC: Parallelizing Compiler for Parallel Computer ADENART, ” Joint Symposium on Parallel Processing’ 91, pages 293–300, May 1991 (in Japanese).
H. Kadota et al., “Parallel Computer ADENART-Its Architecture and Application-, ” Proc. 1991 International Conference on Supercomputing,pages 1–8, June 1991.
K. Kaneko et al., “A VLSI RISC with 20MFLOPS Peak, 64bit Floating Point Unit, ”IEEE J. Solid-State Circuit, 24(5): 1331–1340, October 1989.
Y. Nakakura et al., “A Versatile Data Transfer Control Unit for a Parallel Processor System, ” Digest 1989 Symposium on VLSI Circuits, pages 13–14, 1989.
T. Nogi, “Parallel Computation on ADENA, ” D.J. Evans et al. (eds.), Parallel Computing’ 91, pages 619–626, 1992.
T. Nogi, “Parallel Computation Model PB vs ADEPS, ” Bulletin for JSIAM, 3(l):29–46, 1993 (in Japanese).
High Performance Fortran Forum, DRAFT High Performance Fortran Language Specification, Ver. 1.0, 1993.
T. Nogi, “ADENA Computer IV, ” Mem. Fac. Eng. Kyoto Univ., 55(1):21–36, 1993.
Charles Koelbel, “Compile-Time Generation of Regular Communications Patterns, ” Supercomputing’91, 1991.
Philip Hatcher and Michael Quinn, Data-Parallel Programming on MIMD Computers, Cambridge, MA, MIT Press, 1991.
Michael Wolfe, personal communication, 1993.
J. Li and M. Chen, “Compiling Communication-Efficient Programs for Massively Parallel Machines, ” IEEE Trans. Parallel and Distributed Systems, 2, 1991.
Seema Hiranandani, Ken Kennedy, and Chau-Wen Tseng, “Compiling Fortran D for Distributed-Memory Machines, ” Communications of the ACM, 35(8):66–80, August 1992.
Joseph Fisher, “Trace Scheduling: A Technique for Global Microcode Compaction, ” IEEE Trans. Computers, 30(7), 1981.
G. Geist and V. Sunderam, “Network Based Concurrent Computing on the PVM System, ” Technical Report TM-11760, Oak Ridge National Laboratory, Oak Ridge, Tennessee 37831, June 1991.
Jack Dongarra, Rolf Hempel, Anthony Hey, and David Walker, “A Proposal for a User-Level, Message-Passing Interface in a Distributed Memory Environment, ” Technical Report TM-12231, Oak Ridge National Laboratory, Oak Ridge, Tennessee 37831, January 1993.
T. Imamura, High-Speed Eigenvalue Computation Method on MPP, Master’s thesis, Engineering Division, Kyoto University, 1993 (in Japanese).
D. Bailey, J. Barton, T. Lasinski, and H. Simon, “The NAS Parallel Benchmarks, ” Report RNR-91-002, Revision 2, NASA Ames Research Center, 1991.
D.H. Bailey and E. Barszcz, “NAS Parallel Benchmark Results, ” IEEE Parallel & Distributed Technology, 43–51, 1993.
S. Odanaka et al., “Three-Dimensional Device Simulation on A Super Parallel Computer: ADENA, ” Proc. 7th VLSI Process/Device Modeling Workshop, pages 122–125, August 1990.
S. Odanaka et al., “Massively Parallel Computation Using A Splitting-UP Operator Method For A Three-Dimensional Device Simulation, ” Technical report, IEICE, October 1992.
T. Okamoto et al., “Applications of Parallel Computer ADENART to Simulations, ” National Technical Report, 39(1): 115–120, February 1993.
Hans Zima, Peter Brezany, Barbara Chapman, Piyush Mehrotra, and Andreas Schwald, “Vienna Fortran-a Language Specification-, ” Technical report, ICASE NASA Langley Research Center, Hampton, Virginia 23665, March 1992.
Charles Koelbel and Piyush Mehrotra, “Compiling Global Name-Space Parallel Loop for Distributed Execution, ” IEEE Trans. Parallel and Distributed Systems, 2(4), 1991.
Parasoft Corporation, “Express Version 1.0: A Communication Environment for Parallel Computers, ” Technical report, Parasoft, 1988.
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© 1995 Springer Science+Business Media Dordrecht
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Zaiki, K., Wakatani, A., Okamoto, T., Kaneko, K., Nogi, T. (1995). Parallel Programming Language Adetran. In: Bic, L.F., Nicolau, A., Sato, M. (eds) Parallel Language and Compiler Research in Japan. Springer, Boston, MA. https://doi.org/10.1007/978-1-4615-2269-0_18
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DOI: https://doi.org/10.1007/978-1-4615-2269-0_18
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