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Digital VLSI Neuroprocessors

  • Bing J. Sheu
  • Joongho Choi
Part of the The Springer International Series in Engineering and Computer Science book series (SECS, volume 304)

Abstract

In this chapter, various design examples of digital VLSI neuroprocessors are described. The information in Connected Network of Adaptive Processors (CNAPS) from Adaptive Solutions Inc. provides an entire design process of a general-purpose neuroprocessor from the processing element design to the high-level architecture. The MA-16 chip and SYNAPSE-X system from Siemens Corporation are based on a detailed architecture of the systolic computation. The Ni10000 chip is based on a dedicated-learning architecture, the radial basis function (RBF) network. In addition, other types of digital VLSI neural network implementations are presented with special emphasis on their unique characteristics.

Keywords

Radial Basis Function Systolic Array Register File Elementary Chain Systolic Architecture 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer Science+Business Media New York 1995

Authors and Affiliations

  • Bing J. Sheu
    • 1
  • Joongho Choi
    • 2
  1. 1.University of Southern CaliforniaUSA
  2. 2.IBM Thomas J. Watson Research CenterUniversity of Southern CaliforniaUSA

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