Modeling Chip/Package Power Distribution

Abstract

The power bus that interconnects the switching and non-switching functions on the chip is a major source of coupling between widely separated circuits. Switching return currents take the path of least impedance which is often an on-chip path through the power rails. The presence of on-chip decoupling capacitance distributed on the bus can lessen the amount of bus fluctuation due to these switching currents. The simple discussion that follows assumes that the bus is routed on a metal level but busses are often routed or strapped by salicided polysilicon, silicon, or diffused areas as well. Figure 8.1 shows one rail of a power bus in a random or tree power grid structure. There are two switching functions and two non-switching or quiet circuit functions. There is a single chip pad for the supply rail for both switching and non-switching functions. There is on-chip resistive bus drop which provides coupling between switching and non switching functions in addition to the inductive power bounce due to the package inductance connected to the chip power pad. The additional on-chip resistive coupling, which can be substantial, makes this approach usually undesirable. Sometimes additional bus resistance can be beneficial in specific area where it tends to damp RLC ringing of the power bus. The tree power bus scheme usually requires minimum metal area for the bus but must be hand crafted for each design. There is at least one automatic power supply bus routing tool available that routes the bus based on analog signal integrity constraints.[8.13] Figure 8.1