Substrate Resistance Extraction for Large Circuits
In Chapter 6 we discussed a modeling strategy for substrates with a heavily-doped bulk and a lightly doped epitaxial layer. The advantage of the single node model for such substrates is that, once characterized for a particular process it can readily be used for any circuit structure that uses the same process, irrespective of size. Unfortunately the model does not extend to processes which do not have a heavily-doped bulk which is in effect a collector and distributor of stray electrons and holes. On the other hand, the dc macromodeling technique of Chapter 4 can be used for any Silicon process. The problem with the latter approach however, is that it becomes computationally expensive as the size of the circuit to be simulated increases. In this chapter we will introduce techniques that allow for the numerical computation (extraction) of substrate resistance for large circuit structures.
KeywordsSimulation Technique Boundary Node NMOS Transistor External Node Large Circuit
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