Substrate Resistance Extraction for Large Circuits

  • Nishath K. Verghese
  • Timothy J. Schmerbeck
  • David J. Allstot
Part of the The Springer International Series in Engineering and Computer Science book series (SECS, volume 302)


In Chapter 6 we discussed a modeling strategy for substrates with a heavily-doped bulk and a lightly doped epitaxial layer. The advantage of the single node model for such substrates is that, once characterized for a particular process it can readily be used for any circuit structure that uses the same process, irrespective of size. Unfortunately the model does not extend to processes which do not have a heavily-doped bulk which is in effect a collector and distributor of stray electrons and holes. On the other hand, the dc macromodeling technique of Chapter 4 can be used for any Silicon process. The problem with the latter approach however, is that it becomes computationally expensive as the size of the circuit to be simulated increases. In this chapter we will introduce techniques that allow for the numerical computation (extraction) of substrate resistance for large circuit structures.


Simulation Technique Boundary Node NMOS Transistor External Node Large Circuit 
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    N.K. Verghese and D.J. Allstot, “Simulation of Substrate Coupling in Mixed-Mode VLSI Circuits,” SRC-CMU CAD Center Tech. Report No. CMUCAD 93–02.Google Scholar
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    D.K. Su, M.J. Loinaz, S. Masui and B.A. Wooley, “Experimental Results and Modeling Techniques for Substrate Noise in Mixed-Signal Integrated Circuits, ”IEEE Journal of Solid State Circuitsvol. 28, no. 4, April 1993.Google Scholar

Copyright information

© Springer Science+Business Media New York 1995

Authors and Affiliations

  • Nishath K. Verghese
    • 1
  • Timothy J. Schmerbeck
    • 2
  • David J. Allstot
    • 1
  1. 1.Carnegie Mellon UniversityUSA
  2. 2.IBM. RochesterUSA

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