Abstract
Bulk P- wafer CMOS and BiCMOS processes are the most common and inexpensive in use today. Typical resistivity is 10 ohm-cm and ties to substrate are required to be distributed across the chip to prevent latch-up. NMOS and Bipolar processes do not require distributed substrate ties for latch-up protection and thus have more freedom in controlling substrate noise. Logic families found in NMOS and Bipolar processes are generally less noisy than those found in CMOS processes. Some CMOS processes use p+ buried layers to relax the spacing requirements of substrate contacts to prevent latchup, but the treatment is essentially the same as for standard CMOS processes. Backside contacts are not sufficient to prevent against latch-up alone even when the chip is thinned to 200 microns thick.
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© 1995 Springer Science+Business Media New York
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Verghese, N.K., Schmerbeck, T.J., Allstot, D.J. (1995). Controlling Substrate Coupling in Bulk P- Wafers. In: Simulation Techniques and Solutions for Mixed-Signal Coupling in Integrated Circuits. The Springer International Series in Engineering and Computer Science, vol 302. Springer, Boston, MA. https://doi.org/10.1007/978-1-4615-2239-3_10
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