Characterizing Inductance Effects in RLC Trees

Abstract

The importance of on-chip inductance for single lines has been characterized in [50]-[52] and [69] (see Chapter 5). However, nets in an integrated circuit are often structured as a tree rather than as a single line. Also, the clock distribution network, which is common to all synchronous digital circuitry, is typically tree structured. The performance of an integrated circuit therefore heavily depends upon the design of the clock distribution network where the most accurate interconnect models are required. It is shown in this chapter that a branch of a tree cannot be treated as a single line for the purpose of evaluating inductance effects. Rather, the entire tree should be examined for inductance effects as a single structure since a large interaction occurs among the different branches. It is therefore shown that applying a single line analysis to an RLC tree can cause misleading conclusions.