Equivalent Elemore Delay for RLC Trees

Abstract

An interconnect line in a digital integrated circuit is in general structured like a tree or a zigzag line rather than like a single continuous line as shown in Figure 7.1. Thus, the process of characterizing signal waveforms in tree and zigzag structured interconnect is of primary importance. One of the more popular delay models used within industry for analyzing the temporal properties of RC trees is the Elmore delay model [74], [75]. Despite not being highly accurate, the Elmore delay is widely used by industry for fast delay estimation. With IC’s composed of tens of millions of gates it is often impractical to use highly accurate, time consuming methods to evaluate the delay at each node in a circuit. The Elmore delay model is therefore used to quickly estimate the relative delays of different paths in the circuit, permitting more exhaustive timing simulations to be performed for only the critical paths. Also, the Elmore delay is widely used as a delay model for the synthesis of digital integrated circuits such as buffer insertion in RC trees and wire sizing [26]-[34].