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Wafer-Level Test

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Abstract

Successful development and manufacture of semiconductor components is highly dependent on test verification at several critical steps throughout the process and at multiple levels of packaging. An effective test methodology spans a broad range of products, diverse test systems and product-handling equipment, and encompasses several test techniques. A reliable and cost-effective product contacting method is a key requirement for all of these test techniques to be successful.

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References

  1. E. B. Eichelberger and T. W. Williams, “A Logic Design Structure for LSI Testability,”Proceedings ACM/IEEE 14th Design Automation Conf., pp. 462–468, June 1977.

    Google Scholar 

  2. W. Needham, C. Prunty and E. H. Yeoh, “High Volume Microprocessor Test Escapes, An Analysis of Defects Our Tests Are Missing,” Proceedings International Test Confer 11. ence, pp. 25–34, Oct. 1998.

    Google Scholar 

  3. D. Genin and M. Wurster, “Probing Considerations in C4 Testing of IC Wafers,” International Journal of Microelectronics and Electronic Packaging, vol. 15(4): p. 1, 1992.

    Google Scholar 

  4. R. Bove, “Probe Contactors Having Buckling Beam Probes,” U.S. Patent 3,806,801 (Apr. 23, 1974).

    Google Scholar 

  5. H. Byrnes and R. Wahl, “Contact for an Electrical Contactor Assembly,” U.S. Patent 4,027,935 (June 7, 1977).

    Google Scholar 

  6. A. H. Cottrell, The Mechanical Properties of Matter, New York: John Wiley and Sons, 1964, p. 131.

    Google Scholar 

  7. S. Timoshenko, Strength of Materials, Part 2, New York: D. Van Nostrand Co., 1940, p. 184.

    Google Scholar 

  8. S. Timoshenko and Young, Elements of Strength of Materials, New York: D. Van Nostrand Co., 1968, p. 268.

    Google Scholar 

  9. E. Sechiel, Elasticity in Engineering, New York: Dover Publication, 1968, p. 233.

    Google Scholar 

  10. G. Barsotti, S. Tremaine and M. Bonham, “Very High Density Probing,” Proceedings International Test Conference, p. 608, Oct. 1988.

    Google Scholar 

  11. S. P. Athan, D. C. Keezer and J. Mckinley, “High Frequency Wafer Probing and Power Supply Resonance Effects,” Proceedings International Test Conference, p. 1069, Oct. 1991.

    Google Scholar 

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Karl J. Puttlitz Paul A. Totta

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© 2001 Springer Science+Business Media New York

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Das, G., Motika, F., Atwood, E. (2001). Wafer-Level Test. In: Puttlitz, K.J., Totta, P.A. (eds) Area Array Interconnection Handbook. Springer, Boston, MA. https://doi.org/10.1007/978-1-4615-1389-6_3

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  • DOI: https://doi.org/10.1007/978-1-4615-1389-6_3

  • Publisher Name: Springer, Boston, MA

  • Print ISBN: 978-1-4613-5529-8

  • Online ISBN: 978-1-4615-1389-6

  • eBook Packages: Springer Book Archive

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