Abstract
Plastic Ball Grid Array (PBGA) packages are modules constructed utilizing standard printed circuit card and board technologies. The typical PBGA substrate is a thin (less than 0.035 inches) laminate similar to card technologies used for personal computers. Although the interconnections between a chip and substrate are typically wire bonds, flip-chip dice can be attached to PBGA packages as well. PBGA technologies also support chip scale packaging (CSP) discussed in Chapters 18 and 23.
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References
References
JEDEC, Electronic Industries Association, 2500 Wilson Blvd.,Arlington Va, 22201–3834,http://www.JEDEC.org.
Electronic Industries Association, JEDEC Outline MS-034 Plastic Ball Grid Array Family Registration, 2500 Wilson Blvd.,Arlington Va, 22201–3834, http://www.JEDEC.org.
Electronic Industries Association, JEDEC Outline MO-192 Low Profile Ball Grid Array Family, 2500 Wilson Blvd.,Arlington Va,22201–3834,http://www.JEDEC.org.
Electronic Industries Association, JEDEC STD 95–1–14 Ball Grid Array Package, 2500 Wilson Blvd.,Arlington Va,22201–3834,http://www.JEDEC.org.
B. Freyman and R. Pennisi, “Overmolded Plastic Pad Array Carriers (OMPAC): A Low Cost, High Interconnect Density IC Packaging Solution for Consumer and Industrial Electronics,” 41st Proceedings Electronic Components and Technology Conference, pp. 176–182, May 1991.
S. E. Lindsey, J. Aday, B. Blood, Y. Guo, R. Hemann, J. Kellar, C. Koehler, J. Liu, V. Sarihan, T. Tessier, L. Thompson and E. Young, “JAGS-Pak(TM) Flip-Chip Chip Scale Package Development and Characterizations,” Procceedings 48th Electronic Components and Technology Conference, pp. 511–517, May 1998.
G. Smith, N. Androff, J. Gotro and B. Bedwell, “Advanced Laminate for High Density Interconnect Substrates,” Proceedings Semicon West (San Jose, CA), Session 6, pp. Al—A9, July 1999.
S. Ouimet, J-G. Quintal and G. Robichard, “Wirebonding PBGA Manufacturing Challenges from Fine to Ultrafine Pitch, ” Proceedings SEMI Semiconductor Packaging Symposium, SEMICON West (San Jose, CA) pp. Dl—D9, July 1998.
M. J. Kuzawinski and K. J. Blackwell, “Ultra Fine Pitch Wire Bond PBGA’s,” Electronic Packaging and Production, vol. 37 (12), pp. 56–62, Sept. 1997.
I. Memis, “MicroBGA on Printed Wiring Boards: Recognizing the Need for Surface Laminar Circuit(tm) MicroVia Capability,” Proceedings Semiconductor Packaging Symposium, Semicon West, pp. F-I—F-8, July 1998.
S. R. Tryzbiak and B. J. McDermott, “Photo-Defined Via Technology: Markets, Process and Applications,” Proceedings Semiconductor Packaging Symposium, Semicon West, pp. G-1—G-9, July 1998.
Peter Elenius, “Flip Chip Bumping for Fine Pitch Applications, ” Proceedings The Eleventh Annual Soldering Technology and Interconnection Symposium, Section 7, Oct. 1998.
M.J. Kuzawinski, “Ultra Fine Pitch Wire Bonds: Applications for the Future,” Proceedings Semicon West (San Jose, CA), Section III, pp. El—E9, July 1998.
Mark J. Kuzawinski, “High Density Wire Bond Packages: Chip Scale and Near Chip Scale PBGAs,” Proceedings International Conference and Exhibition on High Density Packaging and MCMs, pp. 169–174, Apr. 1999.
Electronic Industries Association, JEDEC JESD Standard 99 Glossary of Microelectronic Terms, Definitions and Symbols, 2500 Wilson Blvd., Arlington Va, 22201–3834, http://www.JEDEC.org.
Electronic Industries Association, JEDEC STD A112-A Moisture Induced Stress Sensitivity for Plastic Surface Mount Devices, 2500 Wilson Blvd., Arlington Va, 22201–3834, http://www.JEDEC.org.
Electronic Industries Association, JEDEC JESD Standard 51 High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages, 2500 Wilson Blvd., Arlington Va, 22201–3834, http://www.JEDEC.org.
G. Harman, Reliability and Yield Problems of Wire Bonding in Microelectronics, Reston, VA., ISHM, 1991, p. 28.
T. R. Homa, “Reliability Evaluation of Fine Pitch Wire Bond PBGA’s,” Proceedings SEMI Semiconductor Packaging Symposium, SEMICON West (San Jose, CA), pp. A1—A5, July 1998.
T. R. Homa, “Reliability Evaluation of Laminate MultilayerUltra Fine Pitch Wire Bond Modules,” Proceedings SEMI Semiconductor Packaging Symposium, SEMICON West, pp. Dl—D12 (San Jose, CA).
Y. Pao, X. Song and T. Chung, “Thermal Fatigue of BGA Assemblies in Harsh Environments,” Proceedings SEMI Semiconductor Packaging Symposium, SEMICON West (San Jose, CA), B1—B18, July 1998.
M. J. Kuzawinski, “PBGA Products and Applications,” MicroNews, vol. 4(2), pp. 18–19, 2Q1998.
J. W. Wilson, R. D. Sebesta and A. D’Alisio, “Manufacturing Ultra Fine Line PBGA Substrates in A PWB Factory,” Proceedings ECTC, May 1999.
Recommended Reading
J. Korleski, R. Gorrell, C. Bowen and D. Nodding, “New Composite Organic Dielectric for High Performance Flip Chip Single Chip Packages,” Proceedings ECTC, May 1997.
T. Chung and I. Yee, “Wafer Level Packaging Technology,” Proceedings SEMICON West (San Jose, CA), Session 3, pp. A1—A8, July 1999.
M. Belazzouz and M. Jimarez, “Process Assembly Development for High Density ASIC Flip Chip/Plastic Ball Grid Array Packages,” Proceedings SEMICON West (San Jose, CA), Session 5, pp. Dl—D34, July 1999.
E. Hirt, M. Scheffler and G. Troster, “The Use of Area I/O or a Look on Future Architectures,” Proceedings MCM ‘89 (Denver, CO), pp. 339–344, Apr. 1999.
L. J. Curran, Why Ball Grid Arrays are Picking Up Speed, Semiconductor Business News, CMP Media Inc., http://www.eoenabled.com/edtn/out.asp? n=33586386&i=why+ball+grid+arrays+are+ picking+up+sp/eed&url=http % 3A %2F %2 Fwww%2Esemibiznews %2Ecom%-2Fpub% 2F0997%2Finain %2Ehtm&title=Semiconductor+Business+News+Print+Edition %2C +9%2F97, Sept. 1997.
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Kuzawinski, M.J., Homa, T.R. (2001). Plastic Ball Grid Array. In: Puttlitz, K.J., Totta, P.A. (eds) Area Array Interconnection Handbook. Springer, Boston, MA. https://doi.org/10.1007/978-1-4615-1389-6_15
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DOI: https://doi.org/10.1007/978-1-4615-1389-6_15
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