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Reliability of Die-Level Interconnections

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Area Array Interconnection Handbook

Abstract

At the die level, solder interconnections can fail by a number of failure mechanisms if the stress conditions are severe; i.e., fatigue, corrosion, metal migration, electromigration, creep, and thermomigration. Under normal field conditions, non-encapsulated open-array flip chip solder joints attached to alumina chip carriers exhibit the best reliability in the field among all interconnect methods. This, of course, is the result of following established design rules, process parameters and having a firm understanding of the reliability factors associated with flip chip interconnects. Many of these reliability factors are discussed in this chapter. It is necessary to establish an accelerated test capability so that a relatively long life in the field can be predicted on the basis of short term tests. The validity of the tests is achieved by verifying established semi-empirical models and characteristic parameters, and then are employed to predict the field life of joints.

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Authors and Affiliations

  1. IBM Microelectronics, USA

    Giulio DiGiacomo & Jasvir S. Jaspal

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  1. Giulio DiGiacomo
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  2. Jasvir S. Jaspal
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Karl J. Puttlitz Paul A. Totta

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DiGiacomo, G., Jaspal, J.S. (2001). Reliability of Die-Level Interconnections. In: Puttlitz, K.J., Totta, P.A. (eds) Area Array Interconnection Handbook. Springer, Boston, MA. https://doi.org/10.1007/978-1-4615-1389-6_13

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  • DOI: https://doi.org/10.1007/978-1-4615-1389-6_13

  • Publisher Name: Springer, Boston, MA

  • Print ISBN: 978-1-4613-5529-8

  • Online ISBN: 978-1-4615-1389-6

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