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History of Flip Chip and Area Array Technology

  • Chapter
Area Array Interconnection Handbook

Abstract

The concept of interconnecting a chip to a package in a face-down or “flip chip” orientation is simple enough, and forty years old. The idea of having input-output connections all over the face of a flip chip is also a simple idea, and twenty-five years old. Then, how is it, in the last days of the twentieth century, that the electronics industry finds itself in the midst of a revolution in electronic assembly referred to as flip-chip area-array packaging?

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References

  1. W. H. Kohl, Handbook of Materials and Techniques for Vacuum Devices, eds., New York, Amsterdam, London: Reinhold, 1967.

    Google Scholar 

  2. J. Bardeen and W. H. Brattain, Phys. Rev., 74:p. 230, July 1948.

    Article  Google Scholar 

  3. W. H. Brattain and J. Bardeen, Phys. Rev., 74:p. 231, July 1948.

    Article  Google Scholar 

  4. W. Shockley and G. L. Pearson, Phys. Rev., 74: p. 232, July 1948.

    Article  Google Scholar 

  5. L. P. Hunter, Handbook of Semiconductor Electronics. New York: McGraw-Hill, 1970, pp. 9–19.

    Google Scholar 

  6. O. L. Anderson, H. Christensen and P. Andreatch, “Technique for Connecting Leads to Semiconductors,” Journal of Applied Physics, 28: p. 923, Aug. 1957.

    Article  Google Scholar 

  7. J. M. Goldey, “7C-Evaporation and Alloying to Silicon,” in F. J. Biondi, Transistor Technology, vol. 3, Princeton: Van Nostrand, 1958, p. 231.

    Google Scholar 

  8. B. Selikson and T. A. Longo, “A Study of Purple Plague and its Role in Integrated Circuits,” Proceedings of IEEE, 52: p. 1638, Dec. 1964.

    Article  Google Scholar 

  9. E. Philofsky, “Intermetallic Formation in Gold-Aluminum Systems,” Solid State Electronics, 13: pp. 1391–1399, Oct. 1970.

    Article  Google Scholar 

  10. G. C. Harman, Reliability and Yield Problems of Wire Bonding in Microelectronics, Reston, VA: ISHM, 1989, pp. 141–163, pp. 164–177.

    Google Scholar 

  11. E. Pugh, Building IBM Cambridge: The MIT Press, 1995, pp. 163–182, pp. 263–316.

    Google Scholar 

  12. E. W. Pugh, L. R. Johnson and J. H. Palmer, IBM’s 360 and Early 370 System, Cambridge: The MIT Press, 1991, pp. 48–112, pp. 424476.

    Google Scholar 

  13. E. M. Davis, W. E. Harding, R. S. Schwartz and J. J. Corning, “Solid Logic Technology: Versatile, High Performance Microelectronics,” IBM J. Res Develop., 8: p. 102,1964.

    Article  Google Scholar 

  14. J. A. Perri, H. S. Lehman, W. A. Pliskin and J. Riseman, “Surface Protection of Silicon Devices with Glass Films,” Electrochemical Society Fall Meeting, (Detroit, MI), Oct. 2, 1961.

    Google Scholar 

  15. W. A. Pliskin and E. E. Conrad, “Techniques for Obtaining Uniform Thin Glass Films on Substrates,” Electrochemical Technology, 2: p. 196,1964.

    Google Scholar 

  16. E. Bloch Presentation at IBM, “Solid Logic Technology Program-Objectives and Directions,” Aug. 1,1961. As described by E. Pugh et al. in Ref. [12], p. 75.

    Google Scholar 

  17. D. K. Seto and H. Wing, “High Speed Saw for Dicing Silicon Wafers,” presented at ASME Meeting (New York), NY, 1966.

    Google Scholar 

  18. T. R. Reid (describing the activities of J. Kilby and R. Noyce, the co-inventors of integrated circuits), The Chip, New York: Simon and Schuster, 1984.

    Google Scholar 

  19. “RCA’s New Spectra 70 Series,” Datamation, pp. 34–36, Dec. 1964.

    Google Scholar 

  20. M. Hansen, The Constitution of Binary Phases Diagrams, 2nd Edition, New York: McGraw Hill, 1958, pp. 230–231.

    Google Scholar 

  21. E. Davis, R. McNutt and A. Mones, “Method of Fabricating Microminiature Functional Components,” US Patent 3,292,240, issued Dec. 20, 1966.

    Google Scholar 

  22. P. Totta, “Flip-Chip Solder Terminals,” 21st Electronic Components Conf., p. 275, May 1971.

    Google Scholar 

  23. I. Hymes, R. Sopher and P. Totta, “Terminals for Microminiaturized Devices and Methods of Connecting Same to Circuit Panels,” US Patent 3,303,393 issued Feb. 7,1967.

    Google Scholar 

  24. P. A. Totta and R. P. Sopher, “SLT Device Metallurgy and its Monolithic Extensions,” IBM J of Res and Develop., 13: p. 226, May 1969.

    Article  Google Scholar 

  25. L. E Miller, “Controlled Collapse Reflow Chip Joining,” IBM J of Res and Develop.,13: p. 239, May 1969. US Patent 3,429,040 issued Feb. 25, 1969.

    Google Scholar 

  26. J. Langdon, C. Karan, R. Pecoraro and P. Totta, “Vapor Depositing Solder” (BLM/ Solder Unimask Process), Patent 3,401,055, issued Sept. 10, 1968.

    Google Scholar 

  27. L. F Miller, “Silver Palladium Fired Electrodes”: Proc. IEEE Electronics Components Conference, pp. 52–64, May 1968.

    Google Scholar 

  28. V. Marcotte and N. G. Koopman, “Palladium Depletion of AgPd Thick Film Electrodes,” Proc. of IEEE Elec. Comp. Conf, pp. 157–164, May 1981.

    Google Scholar 

  29. G. DiGiacomo, J. Gniewek, J. Rizzuto and W. Rosenberg, “AuAgPd Ternary Alloy for Thick Film Electrodes,” Proc. of IEEE Elec. Comp. Conf., pp. 354–356, May 1982.

    Google Scholar 

  30. P. D. Davidse and L. I. Maissel, “RF Sputtering of Insulators,” 3rd Intl. Vacuum Congress (Stuttgart, Germany), July, 1965; “Dielectric Thin Films through RF Sputtering,” Journ. of Appl. Phys., 37: p. 574, 1966.

    Article  Google Scholar 

  31. L. Kuiper, Si-Doped Al Patent, “Method for Providing Electrical Connections to Semiconductor Devices,” Patent 3,382,568 issued May 14,1968.

    Google Scholar 

  32. I. Ames, F. M. D’Heurle and R. Horstman, “Reduction of Electromigration in Aluminum Films by Copper Doping,” IBM J Res. Dev., 14: p. 461,1970.

    Article  Google Scholar 

  33. B. Agusta, P. Bardell and P. Castrucci, “Sixteen Bit Monolithic Memory Array Chip,” IEEE Electron Devices Meeting (Washington, DC), Oct. 1965.

    Google Scholar 

  34. L. Goldman, “Self-Alignment Capability of Controlled Collapse Chip Joining,” Proc. 22nd Elec. Comp. Conf., p. 332, May 1972.

    Google Scholar 

  35. S. Patra and Y. Lee, “Modeling of Self Alignment in Flip Chip Soldering-Part 2; Multichip Solder Joints,” Proc ECTC,pp. 783–788, May 1991.

    Google Scholar 

  36. K. C. Norris and A. H. Landzberg, “Reliability of Controlled Collapse Interconnections,” IBM J. Res Develop., 13: p. 266, May 1969.

    Article  Google Scholar 

  37. L. E Coffin, Jr., “Low-Cycle Fatigue,” Metals Engineering Quarterly, p. 15, Nov. 1963.

    Google Scholar 

  38. L. S. Goldman, “Geometric Optimization of Controlled Collapse Interconnections,” IBM J. Res. Develop., 13: p. 251, May 1969.

    Article  Google Scholar 

  39. B. Landman and R. Russo, “On a Pin versus Block Relationship for Partitions of Logic Graphs,” IEEE Trans. Comput., C-20: p. 1469, 1971.

    Google Scholar 

  40. D. J. Bendz, R. W. Gedney and J. Rasile, “Cost/Performance Single Chip Module,” IBM J. Res. Develop., 26: pp. 278–285,1982.

    Article  Google Scholar 

  41. M. E. Williams, “Production of MCP Chip Carriers,” 40th ECTC,pp. 408–411, May 1990.

    Google Scholar 

  42. A. J. Blodgett, “A Multilayer Ceramic Multichip Module,” IEEE Components Hybrid Manuf. Technol., CHMT-3: p. 634,1980.

    Google Scholar 

  43. A. Oscilowski, SEMATECH, Packaging Subsection, NEMI Roadmap, 1996.

    Google Scholar 

  44. M. P. Lepselter, “Beam Lead Technology,” Bell System Tech J, 45: pp. 233–253, Feb. 1966.

    Google Scholar 

  45. J. M. Smith, invited presentation on “GE Mini-mod TAB Technology,” 21st ECC, May 1971.

    Google Scholar 

  46. G. Dehaine and M. Leclercq, “Tape Automated Bonding, A New Multichip Module Assembly Technique,” Electronic Components Conference Proceedings, pp. 69–73, May 1973.

    Google Scholar 

  47. M. J. Sheaffer, “Wirebonding,” Microelectronics Packaging Handbook, Second Edition, R. Tummala, et al., New York: Chapman & Hall, 1997, pp. 11–186 to 11–217.

    Google Scholar 

  48. M. G. Pecht and L. T. Nguyen, “Plastic Packaging,” Microelectronic Packaging Handbook,Second Edition, Tummala, ed., New York: Chapman & Hall, 1997, pp. 11–394 to 11–508.

    Google Scholar 

  49. J. Lau, Ball Grid Array Technology, New York: McGraw Hill, 1995, p. 144.

    Google Scholar 

  50. T. Caulfield, J. Benenati and J. Acocella, “Surface Mount Array Interconnections for High I/O MCM-C to Card Assemblies,” Proc. of Int’l Con. on Multichip Modules (Denver, CO), pp. 320–325, April 1993.

    Google Scholar 

  51. K. Puttlitz, T. Caulfield and M. Cole, “Effect of Material Properties on the Fatigue Life of Dual Solder (DS) Ceramic Ball Grid Array (CBGA) Solder Joints,” Proc. 45th ECTC, pp. 1005–1010, May 1995.

    Google Scholar 

  52. E M. Hall, “Solder Post Attachment of Ceramic Chip Carriers to Ceramic Film Integrated Circuits,” 31st Electronic Components Conference Proceedings, pp. 172–180, May 1981.

    Google Scholar 

  53. B. T. Clark, “Design of the IBM Thermal-Conduction Module,” Proc. IEEE Hybrids Manuf. Technol., CHMT-4: 1981.

    Google Scholar 

  54. R. C. Chu, U. P. Hwang and R. E. Simons, “Conduction-Cooled Module for High-Performance LSI Devices,” IBM J. Res. Devel., 26(1): pp. 55–56,1982.

    Article  Google Scholar 

  55. T. Redmond, C. Prasad and G. Walker, “Polymide Copper Thin Film Redistribution on Glass Ceramic/Copper Multilevel Substrates,” 41st ECTC Proceedings, pp. 689–692, May 1991.

    Google Scholar 

  56. K. J. Puttlitz, “Flip-Chip Replacement Within the Constraints Imposed by Multilayer Ceramic (MLC) Modules,” J. Electron. Mater., 13 (1): pp. 29–46,1984.

    Article  Google Scholar 

  57. R. R. Tummala, J. U. Knickerbocker, S. H. Knickerbocker, L. W. Herron, R. N. Master, R. W. Nufer, M. O. Niesser, B. M. Kellner,C. H. Perry, J. N. Humenik and T. E Redmond, “High Performance Glass Ceramic/Copper Multilayer Substrate with Thin Film Redistribution,” IBM J. Res. Devel., 36: pp. 889–903, 1992.

    Article  Google Scholar 

  58. D. Edelstein, J. Heidenreich, R. Goldblatt, W. Cote, C. Uzoh, N. Lustig, P. Roper, T. McDevitt, W. Motsiff, A. Simon, J. Dukovic, R. Wachnik, H. Rathore, R. Schulz, L. Su, S. Luce and J. Slattery, “Full Copper Wiring in a Sub-0.25 gm CMOS ULSI Technology,” Tech. Dig. IEEE Electron Devices Mtg.,pp. 773–776, 1997.

    Google Scholar 

  59. G. Katopis, W. Becker, T. Mazzawy, H. Smith, C. Vakirtzis, S. Kuppinger, B. Singh, P. Lin, J. Bartells, Jr., G. Kihlmire, P. Venkatachalam, H. Stoller and J. Frankel, “MCM Technology and Design for the S/390 G5 System,” IBM J. Res. Develop., 43, No. 5/6: pp. 621–650, Sept./Nov. 1999.

    Google Scholar 

  60. F. Nakano, T. Soga and S. Amagi, “Resin Insertion Effect on Thermal Cycle Resistivity of Flip Chip Mounted LSI Devices,” Proceeding of 1987 ISHM Conference, pp. 536–541, Sept. 1987.

    Google Scholar 

  61. D. Suryanarayana, R. Hsiao, T. P. Gall and J. M. McCreary, “Flip Chip Solder Bump Fatigue Life Enhanced by Polymer Encapsulation,” Proc. 40th Elec. Comp. Tech. Conf., pp. 338–344, May 1990.

    Google Scholar 

  62. Y. Tsukada, “Surface Lamilar Circuit and Flip Chip Attach Packaging,” ECTC Proceedings, pp. 22–27, May 1992.

    Google Scholar 

  63. H. L. Heck, J. T. Kolias and J. S. Kresge, “High Performance Carrier Technology,” Proc. 1993 IEPS Conf.,pp. 771–779, June 1993.

    Google Scholar 

  64. J. Korleski, R. Gorrell, C. Bowen and D. Noddin, “New Composite Organic Dielectric for High Performance Flip Chip Single Chip Packages,” 47th ECTC Proceedings, pp. 1015–1021, May 1997.

    Google Scholar 

  65. C. Tytran-Palomaki, R. Stutzman, D. Alcoe, T. Kindl, J. Kresge and J. Libous, “A High Performance, Low Stress, Laminated Ball Grid Array Flip Chip Carrier,” presentation at Semicon West, Session 6 (San Jose, CA), July 14,1999.

    Google Scholar 

  66. B. Freyman and R. Pennisi, “Overmolded Plastic Pad Array Carriers (OMPAC): A Low Cost, High Interconnect Density IC Packaging Solution for Consumer and Industrial Electronics,” Proc. 41st ECTC, p. 176, May 1991.

    Google Scholar 

  67. S. Lindsey, J. Aday, B. Blood, Y. Guo, B. Hemann, J. Kellar, C. Koehler, J. Liu, V. Sarinan, T. Tessier, L. Thompson and B. Yeung, “JACS-Pak’ Flip-Chip Chip Scale Package Development and Characterization,” Proc. 48th ECTC, p. 511, May 1998.

    Google Scholar 

  68. T. DiStefano, “The uBGA as a Chip Size Package,” Proc. Nepcon West `95, pp. 327–333, Feb./Mar. 1995.

    Google Scholar 

  69. T. Houston, “Inside the Newest SONY Camcorder,” Portable Design, p. 28, May 1997.

    Google Scholar 

  70. N. Koopman, Concise Encyclopedia of Semiconducting Materials and Related Technologies, London: Pergamon Press, 1992, pp. 184–187.

    Google Scholar 

  71. M. Ohshima, A. Kenmotsu and I. Ishi, “Optimization of Micro Solder Reflow Bonding for the LSI Flip Chip,” The Second International Electronics Packaging Conference, Nov. 1982.

    Google Scholar 

  72. L. J. Fried, J. Havas, J. S. Lechaton, J. S. Logan, G. Paal and P. Totta, “A VLSI Bipolar Metallization Design with Three-Level Wiring and Area Array Solder Connections,” IBM J. Res. Develop., 26: pp. 362–371, May 1982.

    Article  Google Scholar 

  73. W. C. Ward, “Volume Production of Unique Plastic Surface-Mount Modules for the IBM 80 ms 1-M bit DRAM Chip by Area Wire Bond Techniques,” 39th Electronics Components Conference, pp. 552–557, May 1988.

    Google Scholar 

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  1. IBM Microelectronics, USA

    Paul A. Totta

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Karl J. Puttlitz Paul A. Totta

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Totta, P.A. (2001). History of Flip Chip and Area Array Technology. In: Puttlitz, K.J., Totta, P.A. (eds) Area Array Interconnection Handbook. Springer, Boston, MA. https://doi.org/10.1007/978-1-4615-1389-6_1

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  • DOI: https://doi.org/10.1007/978-1-4615-1389-6_1

  • Publisher Name: Springer, Boston, MA

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