Universal Model for Ring Oscillator Phase Noise
In this chapter, we analyze the phase noise due to both the device noise and power supply/substrate noise. We approach our phase noise model by first providing some experimental comparison between five oscillators with different delay cell topologies in Section 1. Their oscillation frequency and the total power consumed are kept approximately equal for a fair phase noise comparison. Then we present a modified linear model in Section 2 which considers the nonlinear impact of voltage clipping. In Section 3, we define an effective Q factor (Q eff for the ring oscillators with voltage clipping and predict an increase in (Q eff with the advance in the operating speeds of CMOS technologies. In Section 4, we describe the noise up-conversion mechanism due to the bias and frequency control circuits. Then we discuss the impact of the digital switching noise coupled through the shared power supply and substrate in Section 5. Finally we provide some conclusions in Section 6.
KeywordsExpense Sine Librium Aliasing Osin
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