Universal Model for Ring Oscillator Phase Noise

  • Liang Dai
  • Ramesh Harjani
Part of the The Springer International Series in Engineering and Computer Science book series (SECS, volume 708)


In this chapter, we analyze the phase noise due to both the device noise and power supply/substrate noise. We approach our phase noise model by first providing some experimental comparison between five oscillators with different delay cell topologies in Section 1. Their oscillation frequency and the total power consumed are kept approximately equal for a fair phase noise comparison. Then we present a modified linear model in Section 2 which considers the nonlinear impact of voltage clipping. In Section 3, we define an effective Q factor (Q eff for the ring oscillators with voltage clipping and predict an increase in (Q eff with the advance in the operating speeds of CMOS technologies. In Section 4, we describe the noise up-conversion mechanism due to the bias and frequency control circuits. Then we discuss the impact of the digital switching noise coupled through the shared power supply and substrate in Section 5. Finally we provide some conclusions in Section 6.


Phase Noise Flicker Noise Ring Oscillator Delay Cell Voltage Swing 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

Copyright information

© Springer Science+Business Media New York 2003

Authors and Affiliations

  • Liang Dai
    • 1
  • Ramesh Harjani
    • 2
  1. 1.Prominent Communications, Inc.San DiegoUSA
  2. 2.Department of Electrical and Computer EngineeringUniversity of MinnesotaMinneapolisUSA

Personalised recommendations