Abstract
The chip’s processor core implements the ARM V4 instruction set architecture (ISA) [6.1]. The implementation was derived from an RTL behavioral model (provided by ARM Ltd.) which fixed both the ISA as well as the processor core interface. However, both the custom physical implementation of the core, as well as the rest of the microprocessor design, were fully optimized for energy efficiency.
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Burd, T.D., Brodersen, R.W. (2002). Microprocessor and Memory IC’s. In: Energy Efficient Microprocessor Design. Springer, Boston, MA. https://doi.org/10.1007/978-1-4615-0875-5_6
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DOI: https://doi.org/10.1007/978-1-4615-0875-5_6
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