Abstract
While it is important to be aware of energy issues at all levels of the design hierarchy, energy-efficiency optimizations at the level of architectural design generally yield the largest gains. The closer the design approaches to the final physical implementation, the more difficult the gains become because the scope of possible optimizations narrows.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
J. Bunda, et. al., “16-Bit vs. 32-Bit Instructions for Pipelined Architectures”, Proceedings of the 20th International Symposium on Computer Architecture, May 1993, pp. 237–46.
Advanced RISC Machines, Ltd., Introduction to Thumb, Developer Technical Document, Mar. 1995.
J. Bunda, W.C. Athas, and D. Fussell, “Evaluating Power Implications of CMOS Microprocessor Design Decisions”, Proceedings of the 1994 International Workshop on Low-Power Design, Napa Valley, CA, April 1994.
P. Freet, “The SH Microprocessor: 16-Bit Fixed Length Instruction Set Provides Better Power and Die Size”, Proceedings of the Thirty-Ninth IEEE Computer Society International Conference, Mar. 1994, pp. 486–8.
T. Burd, B. Peters, A Power Analysis of a Microprocessor: A Study of an Implementation of the MIPS 3000 Architecture, ERL Technical Report, University of California, Berkeley, 1994.
J. Montanaro, et. al., “A 160MHz 32b 0.5W CMOS RISC Microprocessor”, Proceedings of the Thirty-Ninth IEEE International Solid-State Circuits Conference - Slide Supplement, Feb. 1996, pp. 170–1.
J. Bunda, Instruction-Processing Optimization Techniques for VLSI Microprocessors, Ph.D. Thesis, The University of Texas at Austin, 1993.
A. Chandrakasan, S. Sheng, and R.W. Brodersen, “Low-Power CMOS Digital Design”, IEEE Journal of Solid State Circuits, Apr. 1992, pp. 47384.
R. Gonzalez and M. Horowitz, “Energy Dissipation in General Purpose Processors”, Proceedings of the IEEE Symposium on Low Power Electronics, Oct. 1995, pp. 12–3.
M. Johnson, Superscalar Microprocessor Design, Englewood, NJ: Prentice Hall, 1990.
D. Wall, Limits of Instruction-Level Parallelism, DEC WRL Research Report 93/6, Nov. 1993.
M. Smith, M. Johnson, and M. Horowitz, “Limits on Multiple Issue Instruction”, Proceedings of the Third International Conference on Architectural Support for Programming Languages and Operating Systems, Apr. 1989, pp 290–302.
N. Jouppi and D. Wall, “Available Instruction-Level Parallelism for Superscalar and Superpipelined Machines”, Proceedings of the Third International Conference on Architectural Support for Programming Languages and Operating Systems, Apr. 1989, pp 272–82.
J. Montanaro, et. al., “A 160-MHz 32-b 0.5-W CMOS RISC Microprocessor”, IEEE Journal of Solid State Circuits, Vol. 31, No. 11, Nov. 1996, pp. 1703–14.
V. Tiwari, et. al., “Instruction Level Power Analysis and Optimization of Software”, Journal of VLSI Signal Processing, Vol. 13, Nos. 2/3, Aug/Sep 1996, pp. 223–238.
S. Gaiy, et. al. “The PowerPC 603 Microprocessor: A Low-Power Design for Portable Applications”, Proceedings of the Thirty-Ninth IEEE Computer Society International Conference, Mar. 1994, pp. 307–15.
P. Lowney, et. al., “The Multiflow Trace Scheduling Compiler”, The Journal of Supercomputing, Vol. 7, Boston: Kluwer Academic Publishers, 1993, pp. 51–142.
J. Hennessy, D. Patterson, Computer Architecture: A Quantitative Approach, Morgan Kaufmann, San Francisco, 1995.
J. Rabaey, Digital Integrated Circuits,A Design Perspective, Prentice Hall, Upper Saddle River, NJ, 1996.
J. Bunda, W.C. Athas, and D. Fussell, “Evaluating Power Implications of CMOS Microprocessor Design Decisions”, Proceedings of the 1994 International Workshop on Low-Power Design, Napa Valley, CA, April 1994.
C. Su, A. Despain, “Cache Designs for Energy Efficiency”, Proceedings of the Twenty-Eighth Hawaii International Conference on System Sciences, Jan. 1995, pp. 306–315.
Advanced RISC Machines, Ltd., ARM 8 Data Sheet, Document Number ARM-DDI-0100A-I, Feb. 1996.
Author information
Authors and Affiliations
Rights and permissions
Copyright information
© 2002 Springer Science+Business Media New York
About this chapter
Cite this chapter
Burd, T.D., Brodersen, R.W. (2002). Microprocessor System Architecture. In: Energy Efficient Microprocessor Design. Springer, Boston, MA. https://doi.org/10.1007/978-1-4615-0875-5_3
Download citation
DOI: https://doi.org/10.1007/978-1-4615-0875-5_3
Publisher Name: Springer, Boston, MA
Print ISBN: 978-1-4613-5282-2
Online ISBN: 978-1-4615-0875-5
eBook Packages: Springer Book Archive