Abstract
This paper presents a high performance parallel logic simulator on a PC (Personal Computer) cluster, which is based on a new communication algorithm called event clumping to reduce the number of communications. A logic circuit is divided into sub-circuits and assigned to parallel processors. The event clumping stores events to the buffers located at the outputs of the sub-circuits. Then, the events in the buffers are sorted by the addressee and packed into a message. The null message method is an algorithm to avoid deadlocks that can utilize inherent parallelism. However, it has a problem in which a large number of null messages degrade a system performance. As well as the event clumping can reduce the number of communications, it can eliminate unnecessary null messages when it is applied to the null message method. In this paper, optimization of the communication, organization of the simulator system, and a performance evaluation are described. The results of the evaluation shows that the event clumping can reduce communication overhead drastically, and exhibit excellent speedup ratio. It has been also confirmed that the event clumping accelerated the simulation speed by a factor of 13 to 75.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
Similar content being viewed by others
References
Bailey, M., Brinner, J., and Chamberlain (1994). Parallel logic simulation of vlsi systems. ACM computing surveys, 25(3):255–294.
Baker, W. I., Mathmood, A., and Carison, B. S. (1996). Parallel event-driven logic simulation algorithms: tutorials ans comparative evaluation. IEE Circuits Devices Syst, 143(4):177–185.
Brglez, J., Ellis, J., and Kozminski, K. (1989). Combinational profiles of sequential benchmark circuit. Proc. of the IEEE Int. Symp. on Circuits and Systems, pages 1929–1934.
Chandy, M., Misra, J., and Hass, L. M. (1983). Distributed deadlock detection. ACM Transactions on Computer Systems, 1(9): 144–156.
Geist, A., Beguelin, A., Dongarra, J., Jiang, W., Manchek, R., and Sunderam, V. (1994). PVM: Parallel Virtual Machine A Users’ Guide and Tutorial for Networked Parallel Computing. MIT Press.
Karthik, S. and Abraham, J. (1993). A framework for distributed vlsi simulation on a network of workstations. SIMULATION, 60(2):95–104.
Kim, H. K. and Jean, J. (1998). Parallel optimistic logic simulation with event lookahead. Proc. of Int. Conf. on Parallel Processing, pages 20–27.
Matsumoto, Y. (1994). Applications of the time warp mechanism to lsicad. Proc. of Int. Symp. of Fifth Generation Computer Systems′94, pages 117–124.
Misra, J. (1986). Distributed discrete-event simulation. ACM Computing Surveys, 18(1):39–65.
Murakami, T. and Wada, K. (1995). Parallel logic simulation on a workstation cluster. Proc. of the IEEE Pacific Rim Conf. on Communication, Computers and Signal Processing, pages 268–271.
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2002 Springer Science+Business Media New York
About this chapter
Cite this chapter
Wada, K., Murakami, T., Hamada, Y. (2002). Organization and Evaluation of Parallel Logic Simulator on a PC Cluster. In: Dimopoulos, N.J., Li, K.F. (eds) High Performance Computing Systems and Applications. The Kluwer International Series in Engineering and Computer Science, vol 657. Springer, Boston, MA. https://doi.org/10.1007/978-1-4615-0849-6_25
Download citation
DOI: https://doi.org/10.1007/978-1-4615-0849-6_25
Publisher Name: Springer, Boston, MA
Print ISBN: 978-1-4613-5269-3
Online ISBN: 978-1-4615-0849-6
eBook Packages: Springer Book Archive