Abstract
Providing QoS guarantees in packet-switched networks requires the use of traffic scheduling algorithms in the switches or in the routers. Frame-based Fair Queueing (FFQ), a scheduling algorithm for packet switched networks, has been proposed in the literature. The algorithm has O(1) timestamp computation complexity. This makes it more practical for implementations in both general packet networks with variable packet sizes and in asynchronous transfer mode (ATM) networks with fixed packet sizes. In ATM networks, the available time for completing a scheduling decision is very short. This enforces hardware implementations of the scheduling algorithm. In this paper, we propose a hardware architecture of FFQ suitable for implementation in ATM networks (i.e., over SONET-OC48).
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Fattah, H., El-Kharashi, M.W., Elguibaly, F. (2002). Frame-Based Fair Queueing: A Hardware Design for ATM Networks. In: Dimopoulos, N.J., Li, K.F. (eds) High Performance Computing Systems and Applications. The Kluwer International Series in Engineering and Computer Science, vol 657. Springer, Boston, MA. https://doi.org/10.1007/978-1-4615-0849-6_11
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DOI: https://doi.org/10.1007/978-1-4615-0849-6_11
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