Advertisement

Multiple-Valued Logic Synthesis and Optimization

  • Elena Dubrova
Part of the The Springer International Series in Engineering and Computer Science book series (SECS, volume 654)

Abstract

Some Boolean logic problems can be solved more efficiently in multiple-valued domain. This chapter covers a part of the theory of multiple-valued logic related to applications in CAD. Basic methods for representation and optimization of multiple-valued functions are described.

Keywords

Boolean Function Finite State Machine Boolean Network Arithmetic Circuit Logic Synthesis 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. [1]
    R. L. Ashenhurst, “The decomposition of switching functions,” in Proc. Int. Symp. Theory of Switching, Vol. 29, Part. I, pp. 74–116. 1959.Google Scholar
  2. [2]
    I. Ben Dhaou, E. Dubrova and H. Tenhunen 2001 “Power efficient inter-module communication for digit-serial architectures in deep-submicron technology,” in Proc. 31st Int. Symp. Multiple-Valued Logic, pp. 61–67, May 2001.CrossRefGoogle Scholar
  3. [3]
    R. K. Brayton and S. P. Khatri “Multi-valued logic synthesis,” in Proc. 12th Int. Conf. on VLSI Design, pp. 196–206, Jan. 1999.Google Scholar
  4. [4]
    J. T. Butler (ed), Multiple-valued logic in VLSI, California, IEEE Computer Society, 1991.Google Scholar
  5. [5]
    J. T. Butler, “Multiple-valued logic,” IEEE Potentials, Vol. 14, No. 2, pp. 11–14, April–May 1995.CrossRefGoogle Scholar
  6. [6]
    H. A. Curtis, A New Approach to the Design of Switching Circuits Van Nostrand, Princeton, 1962.Google Scholar
  7. [7]
    M. Davio, J.-P. Deschamps and A. Thayse, Discrete and Switching Functions, Switzerland, McGraw-Hill International Book Company, 1978.zbMATHGoogle Scholar
  8. [8]
    L. Djordjevic. “Application of the Karnaugh map to the minimization of functions in ternary logic,” Automatika Theoretical Supplement, Vol. T.3, No. 1–2, pp. 35–38, Zagreb 1967.Google Scholar
  9. [9]
    G. W. Dueck and D. M. Miller, “Direct search minimization of multiple-valued functions,” in Proc. 18th Int. Symp. Multiple-Valued Logic, pp. 218–225, May 1988.Google Scholar
  10. [10]
    E. V. Dubrova, Y. Jiang and R. K. Brayton, “Minimization of multiple-valued functions in Post algebra” in Proc. of Int. Workshop on Logic Synthesis, pp. 132–138, June 2001.Google Scholar
  11. [11]
    E. V. Dubrova, D. B. Gurov and J. C. Muzio, “Full sensitivity and test generation for multiple-valued logic circuits,” in Proc. of 24th Int. Symp. MVL, pp. 284–289, May 1994.Google Scholar
  12. [12]
    E. V. Dubrova, D. B. Gurov D. B. and J. C. Muzio, “The evaluation of full sensitivity for test generation in MVL circuits,” in Proc. 25th Int. Symp. on MVL, pp. 104–109, May 1995.Google Scholar
  13. [13]
    E. V. Dubrova, J. C. Muzio and B. von Stengel, “Finding composition trees for multiple-valued functions,” in Proc. 27th Int. Symp. on MVL, pp. 19–26, May 1997.Google Scholar
  14. [14]
    E. Dubrova and H. Sack, “Probabilistic verification of multiple-valued functions,” in Proc. 30th Int. Symp. on Multiple-Valued Logic, pp. 461–466, May 2000.Google Scholar
  15. [15]
    E. Dubrova, “Multiple-valued logic in VLSI” Multiple-Valued Logic, An International Journal, 2001, to appear.Google Scholar
  16. [16]
    G. Epstein, “The lattice theory of Post algebras,” Trans. Am. Math. Soc., Vol. 95, No. 2, pp. 300–317, Feb. 1960.CrossRefzbMATHGoogle Scholar
  17. [17]
    G. Epstein, Multiple-valued logic design: an introduction, Bristol and Philadelphia, IOP Publishing, 1993.Google Scholar
  18. [18]
    G.C. Files and M. Perkowski, “New multivalued functional decomposition algorithm based on MDDs,” IEEE Trans. on CAD/ICAS, Vol. CAD-14, No. 9, pp. 1081–1086, Sept. 2000.Google Scholar
  19. [19]
    M. Gao, J.-H. Jiang, Y. Jiang, Y. Li, S. Sinha and R. Brayton, “MVSIS,” in Proc. Int. Workshop on Logic Synthesis, pp. 138–144, June 2001.Google Scholar
  20. [20]
    T. Hanyu, “Challenge of a multiple-valued technology in recent deep-submicron VLSI,” in Proc. 31st Int. Symp. on Multiple-Valued Logic, pp. 241–247, May 2001.CrossRefGoogle Scholar
  21. [21]
    T. Hanyu and M. Kameyama, “A 200 MHz pipelined multiplier using 1.5 V-supply multiple-valued MOS current-mode circuits with dual-rail source-coupled logic,” IEEE Journal of Solid-State Circuits, Vol. 30, No. 11, pp. 1239–1245, Nov. 1995.CrossRefGoogle Scholar
  22. [22]
    L. S. Hsu, H. H. Teh, S. C. Chan and K. F. Loe “Multi-valued neural logic networks,” in Proc. 20th Int. Symp. Multiple-Valued Logic, pp. 426–432, May 1990.Google Scholar
  23. [23]
    S. L. Hurst, “A survey: developments in optoelectronics and its applicability to the multiple-valued logic,” in Proc. 16th Int. Symp. Multiple-Valued Logic, pp. 2179–2188, May 1980.Google Scholar
  24. [24]
    S. L. Hurst, “Multiple-Valued Logic — its status and its future,” IEEE Trans. on Computers, Vol. C-33, No. 12, pp. 1160–1179, Dec. 1984.CrossRefGoogle Scholar
  25. [25]
    Y. Jiang and R. K. Brayton, “Don’t cares and multi-valued logic network minimization,” in Proc. Int. Conf. on Computer-Aided Design, pp. 520–526, Nov. 2000.Google Scholar
  26. [26]
    T. Kam, T. Villa, R. Brayton and A. Sangiovanni-Vincentelli, “Multi-valued decision diagrams: theory and applications,” Multiple-Valued Logic, An International Journal, Vol. 4, No. 1–2, pp. 9–24, 1998.MathSciNetzbMATHGoogle Scholar
  27. [27]
    M. Hiratsuka, T. Aoki and T. Higuchi, “A model of reaction-diffusion cellular automata for massively parallel molecular computing,” in Proc. 31st Int. Symp. on Multiple-Valued Logic, pp. 247–253, May 2001.CrossRefGoogle Scholar
  28. [28]
    R. M. Karp, “Functional decomposition and switching circuit design,” J. Soc. Indust. Appl. Math., Vol. 11, pp. 291–335, Nov. 1963.MathSciNetCrossRefzbMATHGoogle Scholar
  29. [29]
    L. Lavagno, S. Malik, R. Brayton and A. Sangiovanni-Vincentelli, “MIS-MV: optimization of multi-level logic with multiple-valued inputs,” in Proc. Int. Conf. Computer-Aided Design, pp. 560–563, Nov. 1990.Google Scholar
  30. [30]
    S. Liao, S. Devadas and A. Ghosh, “Boolean factorization using multiple-valued minimization,” in Proc. Int. Conf. Computer-Aided Design, pp. 606–611, Nov. 1993.Google Scholar
  31. [31]
    T. Luba, “Decomposition of multiple-valued functions,” in Proc. 25th Int. Symp. on MVL, pp. 256–261, May 1995.Google Scholar
  32. [32]
    J. Łukasiewicz, “O logice trójwartościowej,” Ruch Filozoficzny, Vol. 5, pp. 169–171, 1920.Google Scholar
  33. [33]
    J. J. Lou and J. A. Brzozowski, “A generalization of Shestakov’s functional decomposition method,” in Proc. Int. Symp. on Multiple-Valued Logic, pp. 66–71, May 1999.Google Scholar
  34. [34]
    C. Moraga, “A minimization method for 3-valued logic functions,” in Theory of Machines and Computations, ed: Paz A. and Kohavi Z., New York, Academic, pp. 363–375, 1971.Google Scholar
  35. [35]
    C. Moraga, “Multiple-valued threshold logic.” in Optical computing, digital and symbolic, ed: Arrathoon, New York, Dekker, pp. 161–184, 1989.Google Scholar
  36. [36]
    G. D. De Micheli, R. Brayton and A. Sangiovanni-Vincentelli, “Optimal state assignment for finite state machines,” IEEE Trans. on CAD/ICAS, Vol. CAD-4, No. 3, pp. 269–284, July 1985.Google Scholar
  37. [37]
    J. C. Muzio and D. M. Miller, “On the minimization of many-valued functions,” in Proc. 9th Int. Symp. Multiple-Valued Logic, pp. 294–299, May 1979.Google Scholar
  38. [38]
    J. C. Muzio and T. C. Wesselkamper, Multiple-valued switching theory, Bristol, Hilger, 1986.zbMATHGoogle Scholar
  39. [39]
    E. L. Post “Introduction to a general theory of elementary propositions,” Amer. J. Math., Vol. 43, pp. 163–185, 1921.MathSciNetCrossRefzbMATHGoogle Scholar
  40. [40]
    B. Ricco, G. Torelli, M. Lanzoni, A. Manstretta, H. E. Maes, D. Monatanari and A. Modelli, “Non-volatile multilevel memories for digital applications” in Proc. IEEE, Vol. 86, No. 12, pp. 2399–2421, Dec. 1998.Google Scholar
  41. [41]
    D. C. Rine (ed), Computer science and multiple-valued logic, 2nd edn, Amsterdam, North-Holland, 1984.zbMATHGoogle Scholar
  42. [42]
    P. C. Rosenbloom, “Post algebras I, postulates and general theory,” Amer J. Math., Vol. 64, pp. 167–188, 1942.MathSciNetCrossRefzbMATHGoogle Scholar
  43. [43]
    I. G. Rosenberg, “La structure des fonctions de plusieurs variables sur un ensemble fini,” C. R. Acad. Sci. Paris, Ser. AB, Vol. 260, pp. 3817–3819, 1965.zbMATHGoogle Scholar
  44. [44]
    I. G. Rosenberg, “On closed classes, basic sets and groups,” in Proc. 7th Int. Symp. Multiple-Valued Logic, pp. 1–6, May 1977.Google Scholar
  45. [45]
    R. Rudell and A. Sangiovanni-Vincentelli, “Multiple-valued minimization for PLA optimization,” IEEE Trans. on CAD/ICAS, Vol. CAD-5, No. 9, pp. 727–750, Sept. 1987.Google Scholar
  46. [46]
    T. Sasao, “Ternary decision diagrams: survey,” in Proc. 27th Int. Symp. Multiple-Valued Logic, pp. 241–250, May 1997.Google Scholar
  47. [47]
    T. Sasao, “Multiple-valued logic and optimization of programmable logic arrays,” IEEE Computer, Vol. 21, pp. 71–80, 1988.CrossRefGoogle Scholar
  48. [48]
    T. Sasao, Switching Theory for Logic Synthesis, Kluwer Academic Publishers, 1999.Google Scholar
  49. [49]
    K. Shimabukuro and C. Zukeran, “Reconfigurable current-mode multiple-valued residue arithmetic circuits,” in Proc. 28th Int. Symp. Multiple-Valued Logic, pp. 282–287, May 1998.Google Scholar
  50. [50]
    K. C. Smith, “The prospects for multivalued logic: A technology and applications view,” IEEE Trans. om Computers, Vol. C-30, No. 9, pp. 619–634, Sept. 1981.CrossRefGoogle Scholar
  51. [51]
    W. R. Smith, “Minimization of multiple-valued functions,” in Computer science and multiple-valued logic, ed: Rine, North-Holland, Amsterdam, 1984.Google Scholar
  52. [52]
    F. Somenzi, CUDD: CU Decision Diagram Package, Release 2.3.0, University of Colorado at Boulder, 1998.Google Scholar
  53. [53]
    The VIS Group, “VIS: A system for Verification and Synthesis,” in Proc. 8th Int. Conf. on Computer Aided Verification, Springer Lecture Notes in Computer Science, ed: Alur and Henzinger, Vol. 1102, New Brunswick, NJ, pp. 428–432, 1996.Google Scholar
  54. [54]
    B. von Stengel, Eine Dekompositionstheorie für mehrstellige Funktionen Mathematical Systems in Economics, Vol. 123, Anton Hain, Frankfurt, 1991.Google Scholar
  55. [55]
    H. M. Wang, C. L. Lee and J. E. Chen, “Factorization of Multiple-Valued Functions,” 25th Int. Symp. on Multiple-Valued Logic, pp. 164–169, May 1995.Google Scholar

Copyright information

© Springer Science+Business Media New York 2002

Authors and Affiliations

  • Elena Dubrova

There are no affiliations available

Personalised recommendations