Turbo Codes pp 81-104 | Cite as

Demystifying the Fang-Buda Algorithm

Boosting the block turbo decoding
  • Alexandre Giulietti
  • Bruno Bougard
  • Liesbet Van der Perre


After the breakthrough caused by the introduction of Convolutional Turbo Codes (CTCs) by Berrou and Glavieux [1], extensive consolidation work has led to the publication by Joachim Hagenauer of the so-called Turbo Principle [2] The latter actually generalize the principle underlying Berrou’s Turbo Codes to the decoding of any kind of concatenated error correcting code. In 1994, one year after Berrou’s landmark paper, Pyndiah proposed to decode iteratively Forney Jr.’s Block Product Codes [3, 4], as introduced in Chapter 1 of this book as Serially Concatenated Block Codes or Block Turbo Codes (BTCs).


Block Code Turbo Code Pipeline Stage Memory Architecture Extrinsic Information 
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  1. [1]
    C. Berrou, A. Glavieux and P. Thitimajshima, “Near Shannon Limit Error Correcting Coding and Decoding: Turbo Codes”, in proc. IEEE International Conference on Communication, Geneva, Switzerland, May 1993, Vol. 2/3, pp. 1064–1071Google Scholar
  2. [2]
    J. Hagenauer, “The Turbo Principle: Tutorial Introduction and State of the Art”, in proc. International Symposium on Turbo Codes, Brest, France, 1997Google Scholar
  3. [3]
    Forney, G., Jr., “Burst-Correcting Codes for the Classic Bursty Channel”, in IEEE Transactions on Communications, Oct 1971, Vol. 19, Issue. 5, pp. 772–781Google Scholar
  4. [4]
    R. Pyndiah, A. Glavieux, A. Picart and S. Jacq, “Near Optimal Decoding of Product Codes”, in proc. IEEE GLOBECOM’94, San Francisco, Nov. — Dec. 1994, Vol 1/3, pp. 339–343Google Scholar
  5. [5]
    A. Berthet, A, J. Fang, F. Buda, E. Lemois, P. Tortelier, “A comparison of SISO algorithms for iterative decoding of multidimensional product codes” in proc. Vehicular Technologies Conference, Tokyo, Japan, Spring 2000, Vol. 2, pp 1021–1025Google Scholar
  6. [6]
    S. Lin, D. J. Costello, Jr., “Error Control Coding — Fundamentals and Applications”, Prentice-Hall, 1983Google Scholar
  7. [7]
    J. G. Proakis, “Digital Communications”, McGraw-Hill International Editions, Third Edition, 1995Google Scholar
  8. [8]
    S. Benedetto and E. Biglieri, “Principles of digital transmission with wireless applications”, Kluwer Academic Publishing, 1999zbMATHGoogle Scholar
  9. [9]
    D. Chase, “A Class of Algorithms for Decoding Block Codes with Channel Measurement Information”, in IEEE Trans. Inform. Theory, Jan. 1972, Vol. IT-18, pp. 170–182MathSciNetzbMATHCrossRefGoogle Scholar
  10. [10]
    C. Argon and S. W. McLaughlin, “A Parallel Decoder for Low Latency Decoding of Turbo Product Codes”, in IEEE Communication Letters, Vol. 6, NO. 2, Feb 2002, pp 70–72CrossRefGoogle Scholar
  11. [11]
    AHA, “AHA4540 Astro-OC3 155 Mb/s Turbo Product Code Encoder/Decoder”, preliminary data sheet,
  12. [12]
    Xilinx, “Parametrizable Turbo Product Code (TPC) Encoder and Decoder for Virtex-II and Virtex-II PRO”,
  13. [13]
    C-Y Huang, G-W Yu, Bin-DA Liu, A hardware design approach for merge-sorting networks, in proc. IEEE International Symposium on Circuits and Systems, Sydney, May 2001,Google Scholar
  14. [14]
    F. Cathoor, S. Wuytack, E. de Greef, F. Balasa, L. Nachtergaele, A. Vandecapelle, “Custom Memory Management Methodology, Exploration of Memory Organization for Embedded Multimedia System Design”, Kluwer Academic Publishers, 1998Google Scholar
  15. [15]
    E. Brockmeyer, A. Vandecappelle, S. Wuytack, F. Catthoor, “Low power storage cycle budget distribution tool support for hierarchical graphs”, in proc. 13th international symposium on system synthesis (ISSS), Madrid, Spain, Sept. 2000, pp. 20–22Google Scholar
  16. [16]
    A. Papanikolaou et al., “Global Interconnect Trade-off for technology over Memory Modules to Application Level: Case Study”, 5 th ACM/IEEE Intnl. Workshop. On System Level Interconnect Prediction, Monterey CA, April 2003Google Scholar

Copyright information

© Springer Science+Business Media New York 2004

Authors and Affiliations

  • Alexandre Giulietti
    • 1
  • Bruno Bougard
    • 1
  • Liesbet Van der Perre
    • 1
  1. 1.DESICS DivisionIMECBelgium

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