Interconnect Parasitic Extraction of Resistance, Capacitance, and Inductance

  • Xiaoning Qi
  • Robert W. Dutton


As semiconductor technology continues to scale, wires, not devices, come to dominate the delay, power and area of microprocessors and ASIC designs. Increasing clock frequency combined with growing chip area results in the ratio of global wire delay to gate delay increasing at a super-linear rate. For sub-0.25 μm technology at gigahertz-scale clock frequencies, interconnects may exhibit transmission line behavior. This has spawned the need to accurately model the parasitics — resistance, capacitance and inductance — for on-chip wires.


Transmission Line Ground Plane Mutual Inductance Loop Inductance Test Chip 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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Copyright information

© Springer Science+Business Media New York 2003

Authors and Affiliations

  • Xiaoning Qi
    • 1
  • Robert W. Dutton
    • 1
    • 2
  1. 1.Sun Microsystems, Inc.USA
  2. 2.Stanford UniversityUSA

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