Interconnect Parasitic Extraction of Resistance, Capacitance, and Inductance

  • Xiaoning Qi
  • Robert W. Dutton

Abstract

As semiconductor technology continues to scale, wires, not devices, come to dominate the delay, power and area of microprocessors and ASIC designs. Increasing clock frequency combined with growing chip area results in the ratio of global wire delay to gate delay increasing at a super-linear rate. For sub-0.25 μm technology at gigahertz-scale clock frequencies, interconnects may exhibit transmission line behavior. This has spawned the need to accurately model the parasitics — resistance, capacitance and inductance — for on-chip wires.

Keywords

Permeability Microwave Resid PCBs Extractor 

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. [1]
    Agilent Technologies, Palo Alto, CA www.agilent.com.
  2. [2]
    Ansoft Corporation, Pittsburgh, PA, Maxwell 2D Parameter Extractor — User’s Reference, Feb. 1993.Google Scholar
  3. [3]
    Ansoft Corporation, Pittsburgh, PA, Maxwell Quick 3D Parameter Extractor —User’s Reference, Dec. 1994.Google Scholar
  4. [4]
    Avant! Corporation, Fremont, CA, Raphael — Reference Manual.Google Scholar
  5. [5]
    Erich Barke, “Line-to-Ground capacitance calculation for VLSI: A comparison”, IEEE Transactions on CAD of Integrated Circuits and Systems, pp.295–298, Vol. 7, No. 2, Feb, 1988.CrossRefGoogle Scholar
  6. [6]
    I. Catt, Digtal Hardware Design, Macmillan, London, 1979.Google Scholar
  7. [7]
    W. H. Chang, “Analytic IC-metal-line capacitance formulas”, IEEE Trans, on Microwave Theory Tech., Vol. 24, pp. 608–611, 1976; also Vol. 25, p. 712, 1977.CrossRefGoogle Scholar
  8. [8]
    David K. Cheng, Field and Wave Electromagnetics, Addison-Wesley Publishing Company, Menlo Park, California, 1983.Google Scholar
  9. [9]
    E. Chiprout, H. Heeb, M.S. Nakhla and A. E. Ruehli, “Simulating 3-D retarded interconnect models using complex frequency hopping (CFH)”, Proceedings of IEEE Int. Conf. on Comp. Aided Des.., pp. 66–72, Nov. 1993.Google Scholar
  10. [10]
    Jane Cullum, Albert Ruehli and Tong Zhang, “A method for reduced-order modeling and simulation of large interconnect circuits and its application to PEEC models with retardation”, IEEE Trans, on Circuits and Systems II, Vol. 47, pp.261–273, Apr. 2000.CrossRefGoogle Scholar
  11. [11]
    A. Deutsch, H. Harrer, C. W. Surovic, G. Hellner, D. C. Edelstein, R. D. Goldbaltt, G. A. Biery, N. A. Greco, D. M. Foster, E. Crabbe, L. T. Su and P. W. Coteus, “Functional high-speed characterization and modeling of a six-layer copper wiring structure and performance comparison with aluminum on-chip interconnections,” IEEE Technical Digest of International Electron Devices Meeting, pp. 295-298, Dec, 1998.Google Scholar
  12. [12]
    A. Deutsch, G. V. Kopcasy, V. A. Ranieri, J. K. Cataldo, E. A. Galli-gan, W. S. Graham, R. P. McGouey, S. L. Nunes, J. R. Paraszczak, J. J. Ritsko, R. J. Serino, D. Y. Shih, and J. S. Wilczynski, “High-speed signal propagation on lossy transmission lines,” IBM J. Research Development, Vol. 34, No. 4, July, 1990.Google Scholar
  13. [13]
    A. Deutsch, G. V. Kopcasy, P. J. Restle, H. H. Smith, G. Katopis, W. D. Becker, P. W. Coteus, C. W. Surovic, B. J. Rubin, R. P. Dunne Jr., T. Gallo, K. A. Jenkins, L. M. Terman, R. H. Dennard, G. A. Sai-Halasz, B. L. Krauter, and D. R. Knebel, “When are transmission-line effects important for on-chip interconnects?”, IEEE Trans. Microwave Theory Tech., vol. 45, No. 10, pp. 1836– 1846, Oct. 1997.CrossRefGoogle Scholar
  14. [14]
    A. Deutsch, Howard H. Smith, Christopher W. Surovic, Gerard V. Kopcsay, David A. Webber, Paual W. Coteus, George A. Katopis, W. Dale Becker, Allan H. Dansky, George A. Sai-Halasz and Phillip J. Restle, “Frequency-dependent crosstalk simulation for on-chip interconnects,” IEEE Transaction on Advanced Packaging, pp. 292–308, Vol. 22, No. 3, Aug., 1999.CrossRefGoogle Scholar
  15. [15]
    A.J. van Genderen and N.P. van der Meijs, “Using articulation nodes to improve the efficiency of finite-element based resistance extraction,” IEEE Proceedings of Design Automation Conference, pp.758–763, 1996.Google Scholar
  16. [16]
    Frederick W. Grover, Inductance calculations – Working formulas and table, Dover Publications, Inc., New York, NY, 1973.Google Scholar
  17. [17]
    R. F. Harrington, Field Computation by Moment Methods, Macmillan, New York, 1968.Google Scholar
  18. [18]
    L. He, N. Chang, S. Lin, and O. S. Nakagawa, “An efficient inductance modeling for on-chip interconnects”, Proceedings of IEEE 1999 Custom Integrated Circuits Conference, pp. 457–460, 1999.Google Scholar
  19. [19]
    J. L. Hess and A. M. O. Smith, “Calculation of potential flow about arbitrary bodies”, Progress in Aerospace Sciences, Vol. 8, pp. 1–138, 1966.CrossRefGoogle Scholar
  20. [20]
    U. S. Inan and A. S. Inan, Engineering Electromagnetics, Addison-Wesley, Menlo Park, CA, pp. 606–607, 1999.Google Scholar
  21. [21]
    M. Kamon, M. J. Tsuk and J. K. White, “FASTHENRY: a multipole-accelerated 3D inductance extraction program”, IEEE Trans. Microwave Theory and Techniques, pp.1750, 1994.Google Scholar
  22. [22]
    A. G. Kandoian et al, Reference Data for Radio Engineers, Howard W. Sams & Co., Inc., New York, the Fifth Edition, 1968.Google Scholar
  23. [23]
    B. Kleveland, X. Qi, L. Madden, R. Dutton and S. Wong, “Line inductance extraction and modeling in a real chip with power grid”, Technical Digest of IEEE International Electron Devices Meeting (IEDM’99), pp. 901, Dec. 1999.Google Scholar
  24. [24]
    B. Krauter and S. Mehrotra, “Layout based frequency dependent inductance and resistance extraction for on-chip interconnect timing analysis”, Proceedings of Design Automation Conference pp. 303–308, 1998.Google Scholar
  25. [25]
    B. Krauter, S. Mehrotra and V. Chandramouli, “Including inductive effects in interconnect timing analysis,” Proceedings of Design Automation Conference, pp. 445–452, June, 1999.Google Scholar
  26. [26]
    Y. L. LeCoz and R. B. Iverson, “A stochastic algorithm for high speed capacitance extraction in integrated circuits”, Solid-State Electronics, Vol. 35, No. 7, pp. 1005–1012, 1992.CrossRefGoogle Scholar
  27. [27]
    S. Lin, N. Chang, and Sam Nakagawa, “Quick on-chip self- and mutual-inductance screen”, Proceedings of IEEE 2000 International Symposium on Quality Electronic Design, pp. 513–520, 2000.Google Scholar
  28. [28]
    Richard E. Matick, Transmission Lines for Digital and Communication Networks, IEEE Press, Piscataway, NJ, 1969.Google Scholar
  29. [29]
    N.V.D. Meijs and J. T. Fokkema, “VLSI circuit reconstruction from mask topology”, Integration, Vol. 2, No. 2, pp. 85–119, 1984.Google Scholar
  30. [30]
    Shannon V Morton, “On-chip inductance issues in multiconductor systems,” Proceedings of Design Automation Conference, June, 1999.Google Scholar
  31. [31]
    K. Nabors and J. White, “FastCap: A multipole accelerated 3-D capacitance extraction program”, IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, pp. 1447–1459, Vol. 10, No. 11, Nov., 1991.CrossRefGoogle Scholar
  32. [32]
    K. Nabors and J. White, “Multipole-Accelerated Capacitance Extraction Algorithm for 3-D Structures with Multiple Dielectrics”, IEEE Transactions on Circuits and Systems - I; Fundamental Theory And Applications, pp. 946–954, Vol. 39, No. 11, Nov., 1992.MATHCrossRefGoogle Scholar
  33. [33]
    Q. Ning, P. M. Dewilde and F. L. Neerhoff, “Capacitance coefficients for VLSI multilevel metalization lines”, IEEE Transactions on Electron Devices, pp.644–649, Vol. 3, No. 34, 1987.CrossRefGoogle Scholar
  34. [34]
    Xiaoning Qi, High Frequency Characterization and Modeling of On-Chip Interconnects and RFIC Wire Bonds, Ph.D. Thesis, Stanford University, June, 2001.Google Scholar
  35. [35]
    Xiaoning Qi, Bendik Kleveland, Zhiping Yu, S. Simon Wong, Robert W. Dutton and Tak Young, “On-Chip Inductance Modeling of VLSI Interconnects”, 2000 IEEE Solid-State Circuits Conference: Digest of Technical Papers, pp. 172–173, Feb. 2000.Google Scholar
  36. [36]
    Xiaoning Qi, Gaofeng Wang, Zhiping Yu, Robert W. Dutton, Tak Young and Norman Chang, “On-chip inductance modeling and RLC extraction of VLSI interconnects for circuit simulation”, IEEE Custom Integrated Circuits conference, pp. 487–490, May, 2000.Google Scholar
  37. [37]
  38. [38]
    P. J. Restle, “High speed interconnects: a designers perspective”, ICCAD’98 Tutorial: Interconnect in high speed designs: problems, methodologies and tools, Nov. 1998.Google Scholar
  39. [39]
    P. J. Restle and Alina Deutsch, “Designing the best clock distribution network”, Digest of technical papers of 1998 Symposium on VLSI Circuits, pp. 2–5, 1998.Google Scholar
  40. [40]
    P. J. Restle, K. A. Jenkins, A. Deutsch and P. W. Cook “Measurement and modeling of on-chip transmission line effects in a 400 MHz microprocessor,” IEEE Journal of Solid-State Circuits Vol. 33, No. 4, April, 1998.Google Scholar
  41. [41]
    P. J. Restle, Albert Ruehli and Steven G. Walker, “Dealing with inductance in high-speed chip design,” 1999 Proceedings of Design Automation Conference, June, 1999.Google Scholar
  42. [42]
    E. B. Rosa and F. W. Grover, “Formulas and tables for the calculation of mutual and self- inductance,” Government Printing Office, 1916.Google Scholar
  43. [43]
    A. E. Ruehli, “Inductance calculations in a complex integrated circuit environment”, IBM J. Research Development, pp. 470–481, Sept. 1972.Google Scholar
  44. [44]
    A. E. Ruehli,“Equivalent circuit models for three-dimensional multi-conductor systems”, IEEE Trans. Microwave Theory and Tech. Vol. 22, No. 3, March, 1974.Google Scholar
  45. [45]
    S. Rusu, S. Tarn, “Clock generation and distribution for the first IA-64 microprocessor”, Digest of 2000 IEEE International Conference on Solid-State Circuits Conference, pp. 176–177, 2000.Google Scholar
  46. [46]
    Y. Saad and M. H. Schultz, “GMRES: a generalized minimal residual algorithm for solving nonsymmetric linear systems” SIAM J. Scientific and Statistical Computing, Vol. 7, pp. 856–869, July, 1986.MathSciNetMATHCrossRefGoogle Scholar
  47. [47]
    T. Sakurai and K. Tamaru, “Simple formulas for two- and three- dimensional capacitance”, IEEE Trans. Electron Devices, vol. 30, pp. 183–185, 1983.CrossRefGoogle Scholar
  48. [48]
    Kenneth L. Shepard and Zhong Tian, “Return-limited inductance: a practical approach to on-chip inductance extraction,” IEEE Transactions on CAD of Integrated Circuits and Systems, pp. 425–346, Vol. 19, No. 4, April 2000.CrossRefGoogle Scholar
  49. [49]
    P. P. Silverster and R. L. Ferrari, Finite Elements for Electrical Engineers, Cambridge University Press, 1983.Google Scholar
  50. [50]
    Hugh H. Skilling, Fundamentals of Electric Waves, John Wiley & Sons, New York, NY, 1948.Google Scholar
  51. [51]
    Hugh H. Skilling, Electric Transmission Lines - Distributed Constants, Theory and Applications, McGraw-Hill Book Company, Inc., New York, NY, 1951.Google Scholar
  52. [52]
  53. [53]
    J. A. Tegopoulos and E. E. Kriezis, “Eddy currents in linear conducting media”, Lesevier Science Publishing Company Inc., New York, NY, 1985.Google Scholar
  54. [54]
    Charles S. Walker, Capacitance, Inductance and Crosstalk Analysis, Artech House, Boston, 1990.Google Scholar
  55. [55]
    W. T. Weeks and L. L. Wu and M. F. McAllister and A. Singh, “Resistive and inductive skin effect in rectangular conductors”, IBM Journal of Research and Development, Vol. 23, No. 6, Nov., 1979.Google Scholar
  56. [56]
    T. Xanthopoulos, D. Bailey, A. Gangwar, M. Gowan, A. Jain and B. Prewitt, “The design and analysis of the clock distribution network for a 1.2 GHz Alpha microprocessor,” 2001 Digest of International Solid-State Circuit Conference, pp.402–403, Feb., 2001.Google Scholar
  57. [57]
    Tak Young, “Practical RC Extraction Techniques”, Tutorial-A at IEEE Design Automation Conference, June, 1998.Google Scholar
  58. [58]
    C. P. Yuan and T. N. Trick, “A simple formula for the estimation of the capacitance of two-dimensional interconnects in VLSI circuits”, IEEE Electron Device Lett., Vol, 3, pp. 391–393, 1982.CrossRefGoogle Scholar
  59. [59]
    A. H. Zemanian, R. R. Tewarson, C.P. Ju and J.F. Jen, “Three-dimension capacitance computations for VLSI/ULSI Interconnects”, IEEE Transactions on CAD of Integrated Circuits and Systems, pp.1319–1326, Vol. 12, No. 8, 1989.CrossRefGoogle Scholar

Copyright information

© Springer Science+Business Media New York 2003

Authors and Affiliations

  • Xiaoning Qi
    • 1
  • Robert W. Dutton
    • 1
    • 2
  1. 1.Sun Microsystems, Inc.USA
  2. 2.Stanford UniversityUSA

Personalised recommendations