Abstract
The Multi-Threshold CMOS (MTCMOS) is a very attractive technique to reduce sub-threshold leakage currents during standby modes by utilizing high-V th power switches (sleep transistors). This technology is straightforward to use, because existing designs can be modified to become MTCMOS blocks by simply adding high-V th power supply switches. In addition, circuits can easily be placed in low leakage states at a fine grain level of control. For this reason, and because the time to market is critical, this technique gained the attention of the industry. Unlike the embedded MTCMOS designs discussed in Chapter 3, circuits employing high-V th sleep transistors do not require the re-designing of the original low-V th block.
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References
J. Kao, A. Chandrakasan, and D. Antoniadis, “Transistor Sizing Issues And Tools For Multi-threshold CMOS Technology,” in Proceedings of the 34th Design Automation Conference, 1997, pp. 409–414.
Y. Ye, S. Borkar, and V. De, “A New Technique for Standby Leakage Reduction in High-Performance Circuits,” in Proceedings of the 1998 Symposium on VLSI Circuits, June 1998, pp. 40–41.
Z. Chen, L. Wei, and K. Roy, “Estimation of Standby Leakage Power in CMOS Circuits Considering Accurate Modeling of Transistor Stacks,” in Proceedings of the International Symposium on Low-Power Electronics and Design, August 1998, pp. 239–244.
J. Kao, S. Narendra, and A. Chandrakasan, “MTCMOS Hierarchical Sizing Based on Mutual Exclusive Discharge Patterns,” in Proceedings of the 35th Design Automation Conference, 1998, pp. 495–500.
J. Kao, Subthreshold Leakage Control Techniques for Low Power Digital Circuits, Ph.D. Thesis, Massachusetts Institute of Technology, May 2001.
S. Mutah, S. Shigematsu, W. Gotoh, and S. Konaka, “Design Method of MTCMOS Power Switch for Low-Voltage High-Speed LSIs,” in Proceedings of Asia and South Pacific Design Automation Conference, pp.113–116, January 1999.
S. Mutah, T. Douseki, Y. Matsuya, T. Aoki, S. Shigematsu, and J. Yamada, “1-V Power Supply High-Speed Digital Circuit Technology with Multi-Threshold Voltage CMOS,” IEEE Journal of Solid-State Circuits, vol. 30, no. 8, pp. 847–853, August 1995.
M. Bohr and Y. El-mansy, “Technology for Advanced High-Performance Microprocessors,” IEEE Transactions on Electron Devices, vol. 45, no. 3, pp. 620–625, March 1998.
M. Anis, S. Areibi, M. Mahmoud, and M. Elmasry, “Dynamic and Leakage Power Reduction in MTCMOS Circuits Using an Automated Efficient Gate Clustering,” in Proceedings of the 39th Design Automation Conference, 2002, pp. 480–485.
M. Anis, S. Areibi, and M. Elmasry, “Design and Optimization of Multi-Threshold CMOS (MTCMOS) Circuits,” IEEE Transactions on Computer-Aìded Design of Integrated Circuits and Systems, vol. 22, no. 10, October 2003 (To appear).
A. Bellaouar and M. Elmasry, Low-Power Digital VLSI Design Circuits and Systems, Kluwer Academics Publications, 1995.
Y. Taur and T. Ning, Fundamentals of Modern VLSI Devices, Cambridge University Press, 1999.
D. Sylvester and C. Hu, “Analytical Modeling and Characterization of Deep-Submicron Interconnect,” Proceedings of the IEEE, vol. 89, no. 5, pp. 634–664, May 2001.
R. Rardin, Optimization in Operations Research, Prentice Hall, Boston, 1998.
S. Mutoh, S. Shigematsu, Y. Matsuya, H. Fukuda, T. Kaneko, and J. Yamada, “A 1-V Multithreshold-Voltage CMOS Digital Signal Processor for Mobile Phone Applications,” IEEE Journal of Solid-State Circuits, vol. 31, no. 11, pp. 1795–1802,1996.
J. Hatler and F. Najm, “A Gate-Level Leakage Power Reduction Method for Ultra Low-Power CMOS Circuits,” in Proceedings of the IEEE Custom Integrated Circuits Conference, 1997, pp. 475–478.
Further Reading
S. Kawashima, T. Shiota, I. Fukushi, R. Sasagawa, W. Shibamato, A. Tsuchiya, and T. Ishihara, “A IV, 10,4mW Low Power DSP Core for Mobile Wireless Use,” IEICE Trans. Electron., VOL. E83-C, NO.l 1, pp. 1739–1749, November 2000.
M. Stan, “CMOS Circuits with Subvolt Supply Voltages,” IEEE Design&Test of Computers, VOL.19, NO.2, pp. 34–43, March-April 2002.
T. Douseki, J. Yamada, and H. Kyuragi, “Ultra Low-power CMOS/SOI LSI Design for Future Mobile Systems,” in Symposium on VLSI Circuits Digest of Technical Papers, pp. 6–9, June 2002.
A. Agrawal, H. Li, and K. Roy, “DRG-Cache: A Data Retention Gated-Ground Cache for Low Power,” in Proc. ACM/IEEE Design Automation Conference, pp.473–478, June 2002.
F. Hamzaoglu and M. Stan, “Circuit-Level Techniques to Control Gate Leakage for sub-lOOnm CMOS,” in Proc. IEEE International Symposium on Low Power Electronics and Design, pp. 60–63, August 2002.
K. Usami, N. Kawabe, M. Koizumi, K. Seta, and T. Furusawa, “Selective Multi-Threshold Technique for High-Performance and Low-Standby Applications”, IEICE Trans. Fundamentals, VOL. E85-A, NO.12, December 2002.
J. Tschanz, S. Narendra, Y. Ye, B. Bloechel, S. Borkar, and V. De, “Dynamic Sleep Transistor and Body Bias for Active Leakage Power Control of Microprocessors,” in International Solid-State Circuits Conference Digest of Technical Papers, pp. 102–103, February 2003.
B. Calhoun, F. Honore, and A. Chandrakasan “Design Methodology for Fine-Grained Leakage Control in MTCMOS,” in Proc. IEEE International Symposium on Low Power Electronics and Design, August 2003. (To appear)
H. Won, K. Kim, K. Jeong, K. Park, K. Choi, and J. Kong, “An MTCMOS Design Methodology and Its Application to Mobile Computing,” in Proc. IEEE International Symposium on Low Power Electronics and Design, August 2003. (To appear)
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Anis, M., Elmasry, M. (2003). MTCMOS Combinational Circuits Using Sleep Transistors. In: Multi-Threshold CMOS Digital Circuits. Springer, Boston, MA. https://doi.org/10.1007/978-1-4615-0391-0_4
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DOI: https://doi.org/10.1007/978-1-4615-0391-0_4
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