An Efficient Microcode-Compiler for Custom DSP-Processors

  • Gert Goossens
  • Jan Rabaey
  • Joos Vandewalle
  • Hugo De Man


In this paper, a microcode compiler for custom DSP-processors is presented. This tool is part of the CATHEDRAL II silicon compiler. Two optimization problems in the microcode compilation process are highlighted: microprogram scheduling and memory allocation. Algorithms to solve them, partly based on heuristics, are presented. Our compiler successfully handles repetitive programs, and is able to decide on hardware binding. In most practical examples, optimal solutions are found. Whenever possible, indications of the complexity are given.


Schedule Algorithm Data Path Memory Allocation Incremental Search Architecture Synthesis 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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Copyright information

© Springer Science+Business Media New York 2003

Authors and Affiliations

  • Gert Goossens
    • 1
    • 4
  • Jan Rabaey
    • 2
    • 4
  • Joos Vandewalle
    • 3
    • 4
  • Hugo De Man
    • 4
  1. 1.Target Compiler TechnologiesBelgium
  2. 2.University of California at BerkeleyUSA
  3. 3.Katholieke Universiteit LeuvenBelgium
  4. 4.IMEC LaboratoryLeuvenBelgium

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