Skip to main content
SpringerLink
Log in

System Design and Analysis Overview

  • Chapter
The Best of ICCAD

  • 641 Accesses

Abstract

At the inception of ICCAD in 1983, system-level design was only a small fish in the EDA pond. In the earlier conferences, only one or at most 2 sessions were dedicated to the topic. This has changed dramatically over the years, and today system design is one of the pillars of the conference. In this paper, we describe the major trends in the field as can be traced from the papers published in the conference as well as other seminal publications. While doing so, we put the papers selected for this volume in the context of the ongoing trends at the time of publication, and their impact on the field. In addition, we provide some background that may help to determine why some proposed approaches did or did not succeed in the long term. We conclude the paper with some reflections on the past and the future.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Log in via an institution
Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD 259.00
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD 329.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info
Hardcover Book
USD 329.99
Price excludes VAT (USA)
  • Durable hardcover edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. G. Goossens, I. Bolsens, B. Lin, and F. Catthoor, “Design of Heterogeneous ICs for Mobile and Personal Communication Systems,” Embedded Tutorial ICCAD, Proc. ICCAD, pp.524–531, Nov. 1994.

    Google Scholar 

  2. P. Lippens, V. Nagasamy, and W. Wolf, “CAD Challenges in Multimedia Computing,” Embedded Tutorial ICCAD, Proc. ICCAD, pp. 502–508, Nov. 1995.

    Google Scholar 

  3. K. Vissers, P. van der Wolf, and G. van Rootselaar, “System Level Design and Debug of High-Performance Embedded Media Systems,” Embedded Tutorial ICCAD, pp. 461–466, Nov. 1999.

    Google Scholar 

  4. J. Rabaey, M. Potkonjak, F. Koushanfar, S. Li, and T. Tuan, “Challenges and Opportunities in Broadband and Wireless Communication Designs,” Embedded Tutorial ICCD, pp. 76–81, Nov. 2000.

    Google Scholar 

  5. ICCAD 2001 Embedded Tutorial (M. Kamon, Moderator), “VLSI MicroSystems: The Power of Many”, Embedded Tutorial ICCAD, Nov 2001.

    Google Scholar 

  6. G. Zimmermann, “The MIMOLA Design System: A Computer Aided Digital Processor Design Method”, Proc. 16th Design Automation Conference, pp. 53–58, 1979.

    Google Scholar 

  7. A. C. Parker, D.E. Thomas, D.P. Siewiorek, M. Barbacci, L. Hafer, G. Leive and J. Kim, “The CMU Design Automation System: An Example of Automated Data Path Design,” Proc. 16th Design Automation Conference, pp. 73–80, 1979.

    Google Scholar 

  8. R. Piloty et al., “The CONLAN Project: Status and Future Plans,” Proc. 19th Design Automation Conference, pp. 202–207, 1982.

    Google Scholar 

  9. M. Barbacci, “The Symbolic Manipulation of Computer Descriptions: An Introduction to ISPS,” Tech. Rep, Dept. of Computer Science, Carnegie-Mellon University, March 1980.

    Google Scholar 

  10. R. Bray ton and C. McMullen, “The Decomposition and Factorization of Boolean Expressions,” Proc. ISCAS Conference, pp. 49–54, May 1982.

    Google Scholar 

  11. R. Brayton et al. “Multiple-Level Logic Optimization System,” Proc. ICCAD, pp. 356–359, Nov. 1986.

    Google Scholar 

  12. R. Brayton, G. Hachtel, L. Hemachandra, A. R. Newton, A.R., A. Sangiovanni-Vincentelli, “A Comparison of Logic Minimization Strategies Using ESPRESSO: An APL Program Package for Partitioned Logic Minimization”, Proc. ISCAS Conf., Rome, pp.42–48, May 1982.

    Google Scholar 

  13. D. Johansen, “Bristle Blocks: a Silicon Compiler,” Proc. 16th Design Automation Conference, pp. 310–313, 1979.

    Google Scholar 

  14. M. Buric, T. Matheson, and O. Christensen, “Embedding Electrical and Timing Constraints in Hierarchical Circuit Layout Generators,” Proc. ICCAD, pp. 3–5, Nov. 1983.

    Google Scholar 

  15. R. K. Brayton, R. Camposano, G. D. Micheli, R. Otten, and J. van Eijndhoven, “The York-town Silicon Compiler System,” in Silicon Compilation (D. Gajski, ed.), pp. 204–310, Addison Wesley, 1988.

    Google Scholar 

  16. H. De Man, J. Rabaey, P. Six, L. Claesen, “CATHEDRAL-II: A Silicon compiler for Digital Signal Processing”, IEEE Design and Test, pp. 13–25, Dec. 1986.

    Google Scholar 

  17. R. Camposano: "Path-Based Scheduling for Synthesis", IEEE Trans. Computer-Aided Design, Vol. 10, pp. 85–93, Jan. 1991.

    Article  Google Scholar 

  18. G. Lakshminarayana, G. Khouri, N.K. Jha:”Wavesched: A Novel Scheduling Technique for Control-Flow Intensive Behavioral Descriptions”, Proc. ICCAD, pp.245–251, Nov. 1997.

    Google Scholar 

  19. G.Goossens, J. Rabaey, J. Vandewalle and H. De Man “An Efficient Microcode-Compiler for Custom DSP-Processors” Proc. ICCAD, pp. 24–27, Nov. 1987.

    Google Scholar 

  20. N. Park, F. J. Kurdahi “Module Assignment and Interconnect Sharing in Register-Transfer Synthesis of Pipelined Data Paths” Proc. ICCAD Conf., pp. 16–19, Nov. 1989.

    Google Scholar 

  21. K.S. Hwang, A.E. Casavant, C. Chang, M.A. d’Abreu, “Scheduling and Hardware Sharing in Pipelined Data-paths”, Proc. ICCAD, pp. 24–27, Nov. 1989.

    Google Scholar 

  22. S.Note, F.Catthoor, J. Van Meerbergen, H.De Man, “Definition and Assignment of Complex Data-Paths suited for High Throughput Applications”, Proc. ICCAD, pp., 6–9 Nov. 1989.

    Google Scholar 

  23. P. Paulin and J. Knight, “Force-Directed Scheduling in Automatic Data Path Synthesis,” Proc. 24th Design Automation Conference, pp. 195–202, June 1987.

    Google Scholar 

  24. W. Verhaegh, P. Lippens, E. Aarts, J. Korst, A. van der Werf, and J. van Meerbergen, “Efficiency Improvements for Force-Directed Scheduling,” Proc. ICCAD, pp. 286–289, Nov. 1992.

    Google Scholar 

  25. J. Vanhoof, I. Bolsens, and H. De Man, “Compiling Multi-Dimensional Data Streams into Distributed DSP ASIC Memory,” Proc. ICCAD, pp. 272–275, Nov. 1991.

    Google Scholar 

  26. I. Ahmad and C. Chen, “Post-Processor for Data Path Synthesis Using Multiport Memories,” Proc. ICCAD, pp. 276–279, Nov. 1991.

    Google Scholar 

  27. P. Lippens, J. van Meerbergen, W. Verhaegh, and A. van der Werf, “Allocation of Multiport Memories for Hierarchical Data Streams,” Proc. ICCAD, pp. 728–731, Nov. 1993.

    Google Scholar 

  28. F. Balasa, F. Catthoor, and H. De Man, “Exact Evaluation of Memory Size for Multi-Dimensional Signal Processing Systems,” Proc. ICCAD, pp. 669–672, Nov. 1993.

    Google Scholar 

  29. D. Kolson, A. Nicolau, and N. Dutt, “Integrating Program Transformations in the Memory-Based Synthesis of Image and Video Algorithms,” pp. 27–30, Nov. 1994.

    Google Scholar 

  30. L. Nachtergaele, V. Tiwari, and N. Dutt, “System and Architecture-Level Power Reduction for Microprocessor-Based Communication and Multimedia Applications,” Proc. ICCAD, pp. 569–572, Nov. 2000.

    Google Scholar 

  31. D. Grant, P. Denyer, and I. Finlay, “Synthesis of Address Generators,” Proc. ICCAD, pp. 108–111, Nov. 1988.

    Google Scholar 

  32. M. Potkonjak and J. Rabaey, “Optimizing Resource Utilization Using Transformations,” Proc. ICCAD, pp. 88–91, Nov. 1991.

    Google Scholar 

  33. A. Chandrakasan, M. Potkonjak, J. Rabaey, and R. Brodersen, “HYPER-LP: A System for Power Minimization Using Architectural Transformations,” Proc. ICCAD, pp. 300–303, Nov. 1992.

    Google Scholar 

  34. A. Raghunathan and N.K. Jha, “An Iterative Improvement Algorithm for Low Power Data Path Synthesis”, Proc. ICCAD, pp. 597–602, Nov. 1995

    Google Scholar 

  35. R. Mehra and J. Rabaey, “Exploiting Regularity for Low-Power Design,” Proc. ICCAD, pp. 166–169, Nov. 1996.

    Google Scholar 

  36. P. Chou, R. Ortega, and G. Borriello, “Synthesis of the Hardware/Software Interface in Microcontroller-Based Systems,” Proc. ICCAD, pp. 488–491, Nov. 1992.

    Google Scholar 

  37. P. Chou, R Ortega, and G. Borriello, “Interface Co-Synthesis Techniques for Embedded Systems,” Proc. ICCAD, pp. 280–287, Nov. 1995.

    Google Scholar 

  38. R. Ortega and G. Borriello, “Communication Synthesis for Distributed Embedded Systems,” Proc. ICCAD, pp. 434–437, Nov. 1998.

    Google Scholar 

  39. J. Sun and R. Brodersen, “Design of System Interface Modules,” Proc. ICCAD, pp. 478–481, Nov. 1992.

    Google Scholar 

  40. B.Lin and S. Vercauteren, “Synthesis of Concurrent System Interface Modules with Automatic Protocol Conversion Generation,” Proc. ICCAD, pp. 101–108, Nov. 1994.

    Google Scholar 

  41. V. Tiwari, S. Malik, and A. Wolfe, “Power Analysis of Embedded Software: A First Step Towards Software Power Minimization,” Proc. ICCAD, pp. 437–445, Nov. 1994.

    Google Scholar 

  42. Y. Li, S. Malik, and A. Wolfe, “Performance Estimation of Embedded Software with Instruction Cache Modeling”, pp. 380–387, Nov. 1995.

    Google Scholar 

  43. R. Ernst and W. Ye, “Embedded Program Timing Analysis Based on Path Clustering and Architecture Classification,” Proc. ICCAD, pp. 598–601, Nov. 1997.

    Google Scholar 

  44. V. Mooney and G. De Micheli, “Real Time Analysis and Priority Scheduler Generation for Hardware-Software Systems with a Synthesized Run-Time System,” Proc. ICCAD, pp. 605–608, Nov. 1997.

    Google Scholar 

  45. Y. Li and W Wolf, “Hardware/Software Co-Synthesis with Memory Hierarchies,” Proc. ICCAD, pp. 430–433, Nov. 1998.

    Google Scholar 

  46. D. Rhodes and W. Wolf, “Co-Synthesis of Heterogeneous Multiprocessor Systems Using Arbitrated Communication,” Proc. ICCAD, pp. 339–342, Nov. 1999.

    Google Scholar 

  47. P. Marwedel And G.Goossens (ed.), “Code Generation for Embedded Processors,” Springer Science+Business Media New York, 1995.

    Google Scholar 

  48. I. Huang and A. Despain, “Generating Instruction Sets and Microarchitectures from Applications,” Proc. ICCAD, pp. 391–396, Nov. 1994.

    Google Scholar 

  49. Hoon Choi, In-Cheol Park, Seung Ho Hwang, Chong-Min Kyung, “Synthesis of Application Specific Instructions for Embedded DSP Software,” Proc. ICCAD, pp. 665–668, Nov. 1998.

    Google Scholar 

  50. Andreas Hoffmann, Oliver Schliebusch, Achim Nohl, Gunner Braun, Oliver Wahlen, Hein-rich Meyr, “Methodology for the Design of Application Specific Instruction Set Processors (ASIP) using the Machine Description Language LISA,” Proc. ICCAD, pp. 625–630, Nov. 2001.

    Google Scholar 

  51. M. Jacome, G. De Veciana and V. Lapinskii, “Exploring Performance Tradeoffs for Clustered VLIW ASIPs,” Proc. ICCAD, pp. 504–510, Nov. 2000.

    Google Scholar 

  52. ICCAD 2001 Embedded Tutorial (E. Sentovic, Moderator), “Platform-Based Design,” Nov. 2001.

    Google Scholar 

  53. Luca P. Carloni, Kenneth L. McMillan, Alexander Saldanha, Alberto L. Sangiovanni-Vincentelli, “A Methodology for Correct-by-Construction Latency Insensitive Design,” Proc. ICCAD, pp. 309–314, Nov. 1999.

    Google Scholar 

  54. E.Lee, A. Sangiovanni-Vincentelli, “Comparing Models of Computation”, Proc. ICCAD, pp. 234–243, Nov. 1996

    Google Scholar 

  55. D. Ziegenbein, K. Richter, R. Ernst, J. Teich, and L. Thiele, “Representation of process mode correlation for scheduling”. Proc. ICCAD pp.54–61, Nov., 1998.

    Google Scholar 

  56. L. Thiele, K. Strehl, Dirk Ziegenbein, Rolf Ernst, J. Teich, “FunState - An Internal Design Representation for Codesign” Proc. ICCAD, pp. 558–565, Nov. 1999.

    Google Scholar 

  57. P.Lieverse, T. Stefanov, P. van der Wolf, E. Deprettere, “System Level Design with Spade: an M-JPEG Case Study “, Proc. ICCAD, pp. 31–38, Nov. 2001

    Google Scholar 

  58. E-Y Chung, L. Benini, G. De Micheli, “Dynamic Power Management Using Adaptive Learning Tree”, Proc. ICCAD, pp. 274–279, Nov. 1999

    Google Scholar 

  59. L. Benini and G. De Micheli, “Dynamic Power Management of Circuits and Systems: Design Techniques and CADTools”, Kluwer, 1997.

    Google Scholar 

  60. A. Sinha, A. Chandrakasan, “Energy Efficient Real-Time Scheduling”, Proc. ICCAD, pp.458–463, Nov. 2001

    Google Scholar 

  61. G.F. Marchioro, J.M. Daveau, A.A.Jerraya, “Transformational Partitioning for Co-Design of Multiprocessor Systems”, Proc. ICCAD. pp, Nov. 1997

    Google Scholar 

  62. C.N.Coehlo, G. De Micheli, “Dynamic Scheduling and Synchronization Synthesis of Concurrent Digital Systems under System-Level Constraints”, Proc. ICCAD, pp. 175–181, Nov. 1994.

    Google Scholar 

  63. S. Haynal, F. Brewer, “Efficient Encoding for Exact Symbolic Automata-Based Scheduling”, Proc. ICCAD, pp. 477–481, Nov. 1998.

    Google Scholar 

Download references

Author information

Authors and Affiliations

  1. Katholieke Universiteit Leuven, Belgium

    Hugo De Man

  2. Interuniversity Microelectronics Center, Leuven, Belgium

    Hugo De Man

  3. University of California at Berkeley, Berkeley, CA, USA

    Jan Rabaey

Authors
  1. Hugo De Man
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Jan Rabaey
    View author publications

    You can also search for this author in PubMed Google Scholar

Editor information

Editors and Affiliations

  1. Cadence Berkeley Labs, Berkeley, CA, USA

    Andreas Kuehlmann

Rights and permissions

Reprints and permissions

Copyright information

© 2003 Springer Science+Business Media New York

About this chapter

Cite this chapter

De Man, H., Rabaey, J. (2003). System Design and Analysis Overview. In: Kuehlmann, A. (eds) The Best of ICCAD. Springer, Boston, MA. https://doi.org/10.1007/978-1-4615-0292-0_8

Download citation

  • DOI: https://doi.org/10.1007/978-1-4615-0292-0_8

  • Publisher Name: Springer, Boston, MA

  • Print ISBN: 978-1-4613-5007-1

  • Online ISBN: 978-1-4615-0292-0

  • eBook Packages: Springer Book Archive

Publish with us

Policies and ethics

Search

Navigation