Timing, Test and Manufacturing Overview

  • Karem A. Sakallah
  • Duncan M. Walker
  • Sani R. Nassif


Timing analysis is concerned with estimating and optimizing the performance of integrated circuits. It encompasses a wide range of activities including physical modeling of transistors and interconnect wires, derivation of analytical and empirical gate and wire delay models, accurate estimation of long- and short-path delays through combinational logic, detection of setup and hold violations in sequential circuits, as well as a variety of combinational and sequential circuit transformations aimed at maximizing operation speed. The three papers reviewed here represent particularly significant contributions to the field of timing analysis and optimization: Brand and Iyengar [4] built the foundation for the field of false-path analysis; Szymanski and Shenoy [33] had the last word on the field of timing verification of latch-based circuits; and Shenoy and Rudell [29] are credited with making retiming viable for industrial-sized circuits.


Path Delay Combinational Logic Sequential Circuit Timing Verification Delay Fault 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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Copyright information

© Springer Science+Business Media New York 2003

Authors and Affiliations

  • Karem A. Sakallah
    • 1
  • Duncan M. Walker
    • 2
  • Sani R. Nassif
    • 3
  1. 1.Electrical Engineering and Computer Science DepartmentUniversity of MichiganAnn ArborUSA
  2. 2.Department of Computer ScienceTexas A&M UniversityCollege StationUSA
  3. 3.IBM ResearchAustinUSA

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