Abstract
We consider the problem of bipartitioning a circuit into two balanced components that minimizes the number of crossing nets. Previously, Kernighan and Lin type (K&L) heuristics, simulated annealing approach, and analytical methods were given to solve the problem. However, network flow techniques were overlooked as viable approaches to min-cut balanced bipartition due to their high complexity. In this paper we propose a balanced bipartition heuristic based on repeated max-flow min-cut techniques, and give an efficient implementation that has the same asymptotic time complexity as that of one max-flow computation. We implemented our heuristic algorithm in a package called FBB. The experimental results demonstrate that FBB outperforms K&L heuristics and analytical methods in terms of the number of crossing nets, and our efficient implementation makes it possible to partition large circuit netlists with reasonable runtime. For example, the average elapsed time for bipartitioning a circuit S35932 of almost 20K gates is less than 20 minutes on a SPARC10 with 32MB memory.
Intel Corp.
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References
R. K. Brayton, R. Rudell, and A. L. Sangiovanni-Vincentelli. MIS: A Multiple-Level Logic Optimization. IEEE Trans. on CAD, pp. 1061–1081, Nov. 1987.
J. Cong and Y. Ding. An Optimal Technology Mapping Algorithm for Delay Optimization in Lookup-Table Based FPGA Designs. In Proc. of the IEEE Int’l Conf. on Computer-Aided Design, pp. 48–53, Nov. 1992.
C.-K. Cheng. Linear Placement Algorithms and Applications to VLSI Design. Networks, vol. 17, pp. 439–464, 1987.
J. Cong, L. Hagen, and A. Kahng. Net Partitions Yield Better Module Partitions. In Proc. of the 29th ACM/IEEE Design Automation Conf., pp. 47–52, 1992.
A. Dasdan and C. Aykanat. Improved Multiple-Way Circuit Partitioning Algorithms. In Int’l ACM/SIGDA Workshop on Field Programmable Gate Arrays, Feb. 1994.
W. E. Donath. Logic Partitioning. In Physical Design Automation of VLSI Systems, pp. 65–86. Preas and Lorenzetti eds., Benjamin/Cummings, 1988.
S. Even. Graph Algorithms. Computer Science Press, 1979.
J. R. Ford and D. R. Fulkerson. Flows in Networks. Princeton University Press, 1962.
C. M. Fiduccia and R. M. Mattheyses. A Linear Time Heuristic for Improving Network Partitions. In Proc. of the ACM/IEEE Design Automation Conf., pp. 175–181, 1982.
R. Gomory and T. C. Hu. Multi-Terminal Network Flows. J. SIAM, vol. 9, pp. 551–570, 1961.
M. Garey and D. S. Johnson. Computers and Intractability: A Guide to the Theory of NP-Completeness. W H. Freeman, 1979.
A. W. Goldberg and R. E. Tarjan. A New Approach to the Maximum Flow Problem. J. SIAM, vol. 35, pp. 921–940, 1988.
J. Hwang and A. El Gamal. Optimal Replication for Min-Cut Partitioning. In Proc. of the IEEE Int’l Conf. on Computer-Aided Design, pp. 432–435, Nov. 1992.
J. Hwang and A. El Gamal. Min-Cut Replication in Partitioned Networks. IEEE Trans. on CAD, vol. 14(1), pp. 96–106, Jan. 1995.
L. Hagen and A. B. Kahng. Fast Spectral Methods for Ratio Cut Partitioning and Clustering. In Proc. of the IEEE Int’l Conf on Computer-Aided Design, pp. 10–13, Nov. 1991.
T. C. Hu and K. Moerder. Multiterminal Flows in a Hypergraph. In VLSI Circuit Layout: Theory and Design, pp. 87–93. Hu and Kuh eds., IEEE Press, 1985.
S. Iman, M. Pedram, C. Fabian, and J. Cong. Finding Uni-Directional Cuts Based on Physical Partitioning and Logic Restructuring. In the 4th ACM/SIGDA Physical Design Workshop, April 1993.
E. Ihler, D. Wagner, and F. Wager. Modeling Hypergraphs by Graphs with the Same Min-Cut Properties. In Info. Proc. Letters, 45, pp. 171–175, 1993.
S. Kirkpatrick, C. D. Gelatt, and M. P. Vecchi. Optimization by Simulated Annealing. Science, pp. 671–680, May 1983.
B. Kernighan and S. Lin. An Efficient Heuristic Procedure for Partitioning of Electrical Circuits. Bell System Technical journal, pp. 291–307, Feb. 1970.
B. Krishnamurthy. An Improved Min-Cut Algorithm for Partitioning VLSI networks. IEEE Trans. on Computers, pp. 438–446, May 1984.
E. Lawler. Combinatorial Optimization: Networks and Matroids. Holt, Rinehart & Winston, New York, 1976.
B. M. Riess, K. Doll, and M. J. Frank. Partitioning Very Large Circuits Using Analytical Placement Techniques. In Proc. 31th ACM/IEEE Design Automation Conf., pp. 646–651, 1994.
L. A. Sanchis. Multiway Network Partitioning. IEEE Trans, on Computers, pp. 62–81, Jan. 1989.
Y. C. Wei and C. K. Cheng. Towards Efficient Hierarchical Designs by Ratio Cut Partitioning. In Proc. of the IEEE Int’l Conf. on Computer-Aided Design, pp. 298–301, Nov. 1989.
H. Yang and D. F Wong. Edge-Map: Optimal Performance Driven Technology Mapping for Iterative LUT Based FPGA Designs. In Proc. of the IEEE Int’l Conf. on Computer-Aided Design, pp. 150–155, Nov. 1994.
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Yang, H.H., Wong, D.F. (2003). Efficient Network Flow Based Min-Cut Balanced Partitioning. In: Kuehlmann, A. (eds) The Best of ICCAD. Springer, Boston, MA. https://doi.org/10.1007/978-1-4615-0292-0_41
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DOI: https://doi.org/10.1007/978-1-4615-0292-0_41
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