Advertisement

TILOS: A Posynomial Programming Approach to Transistor Sizing

  • J. P. Fishburn
  • A. E. Dunlop

Abstract

A new transistor sizing algorithm, which couples synchronous timing analysis with convex optimization techniques, is presented. Let A be the sum of transistor sizes, T the longest delay through the circuit, and K a positive constant. Using a distributed RC model, each of the following three programs is shown to be convex: 1) Minimize A subject to T < K. 2) Minimize T subject to A < K. 3) Minimize AT K . The convex equations describing T are a particular class of functions called posynomials. Convex programs have many pleasant properties, and chief among these is the fact that any point found to be locally optimal is certain to be globally optimal TILOS (Timed Logic Synthesizer) is a program that sizes transistors in CMOS circuits. Preliminary results of TILOS’s transistor sizing algorithm are presented.

Keywords

Critical Path Design Automation Path Delay NAND Gate Drain Capacitance 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. [1]
    V. Agrawal. Synchronous path analysis in MOS circuit simulator. In Design Automation Conf., pages 629–635, 1982.CrossRefGoogle Scholar
  2. [2]
    J. G. Ecker. Geometric programming: methods, computations and applications. SIAM Review, 22(3):338–362, July 1980.MathSciNetzbMATHCrossRefGoogle Scholar
  3. [3]
    L. A. Glasser and L. P. J. Hoyte. Delay and power optimization in VLSI circuits. In Design Automation Conf., pages 529–535, 1984.Google Scholar
  4. [4]
    K. S. Hedlund. Electrical optimization of PLAs. In Design Automation Conf., pages 681–687, 1985.Google Scholar
  5. [5]
    D. D. Hill. SC2: A hybrid automatic layout system. In Int. Conf. on Computer Aided Design, pages 172–174, 1985.Google Scholar
  6. [6]
    N. Jouppi. Timing analysis for nMOS VLSI. In Design Automation Conf., pages 411–418, 1983.Google Scholar
  7. [7]
    C. M. Lee and H. Soukup. An algorithm for CMOS timing and area optimization. IEEE J. of Solid-State Circuits, 19:781–787, October 1984.CrossRefGoogle Scholar
  8. [8]
    T. M. Lin and C. Mead. Signal delay in general RC networks with application to timing simulation of digital integrated circuits. In Conf. on Advanced Research in VLSI, pages 93–99, 1984.Google Scholar
  9. [9]
    M. Matson. Optimization of digital MOS VLSI circuits. In Proc. Chapel Hill Conf. on VLSI, pages 488–491, 1985.Google Scholar
  10. [10]
    J. Ousterhout. Switch-level delay models for digital MOS VLSI. In Design Automation Conf., pages 542–548, 1984.Google Scholar
  11. [11]
    P. Penfield and J. Rubinstein. Signal delay in RC tree networks. In Proc. 2nd Caltech VLSI Conference, pages 269–283, 1981.Google Scholar
  12. [12]
    R. T. Rockafellar. Convex Analysis. Princeton University Press, 1970.zbMATHGoogle Scholar
  13. [13]
    A. E. Ruehli, P. K. Wolff, and G. Goertzel. Analytical power/timing optimization technique for digital system. In Design Automation Conf., pages 142–146, 1977.Google Scholar
  14. [14]
    M. Shoji. Electrical design of BELLMAC-32A microprocessor. In Int. Conf on Circuits and Systems, pages 112–115, 1982.Google Scholar

Copyright information

© Springer Science+Business Media New York 2003

Authors and Affiliations

  • J. P. Fishburn
    • 1
  • A. E. Dunlop
    • 1
  1. 1.AT&T Bell LaboratoriesUSA

Personalised recommendations