TILOS: A Posynomial Programming Approach to Transistor Sizing

  • J. P. Fishburn
  • A. E. Dunlop


A new transistor sizing algorithm, which couples synchronous timing analysis with convex optimization techniques, is presented. Let A be the sum of transistor sizes, T the longest delay through the circuit, and K a positive constant. Using a distributed RC model, each of the following three programs is shown to be convex: 1) Minimize A subject to T < K. 2) Minimize T subject to A < K. 3) Minimize AT K . The convex equations describing T are a particular class of functions called posynomials. Convex programs have many pleasant properties, and chief among these is the fact that any point found to be locally optimal is certain to be globally optimal TILOS (Timed Logic Synthesizer) is a program that sizes transistors in CMOS circuits. Preliminary results of TILOS’s transistor sizing algorithm are presented.


Critical Path Design Automation Path Delay NAND Gate Drain Capacitance 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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Copyright information

© Springer Science+Business Media New York 2003

Authors and Affiliations

  • J. P. Fishburn
    • 1
  • A. E. Dunlop
    • 1
  1. 1.AT&T Bell LaboratoriesUSA

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