Abstract
This paper is concerned with techniques for automatically reducing circuit size and improving testability. In an earlier paper [2], we introuced a new method for circuit optimization based on ideas of global-flow analysis. In this paper, we describe two extensions to the method. The first is a basic improvement in the primary result on which the earlier optimization was based, the second extends the applicability of the method to “conditional” optimizations as well. Together, these enhancements result in improved performance for the original algorithm, as well as the ability to handle designer-specified “don’t cares” and redundancy removal uniformly in the framework of a graph-based synthesis system, such as LSS[8].
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References
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© 2003 Springer Science+Business Media New York
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Berman, C.L., Trevillyan, L.H. (2003). Improved Logic Optimization Using Global-Flow Analysis. In: Kuehlmann, A. (eds) The Best of ICCAD. Springer, Boston, MA. https://doi.org/10.1007/978-1-4615-0292-0_17
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DOI: https://doi.org/10.1007/978-1-4615-0292-0_17
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