Abstract
The increasing demand for “portable” computing and communication, has elevated power consumption to be the most critical design parameter. An automated high-level synthesis system, HYPER-LP, is presented for minimizing power consumption in application specific datapath intensive CMOS circuits using a variety of architectural and computational transformations. The sources of power consumption are reviewed and the effects of architectural transformations on the various power components are presented. The synthesis environment consists of high-level estimation of power consumption, a library of transformation primitives (local and global), and heuristic/probabilistic optimization search mechanisms for fast and efficient scanning of the design space. Examples with varying degree of computational complexity and structures are optimized and synthesized using the HYPER-LP system. The results indicate that an order of magnitude reduction in power can be achieved over current-day design methodologies while maintaining the system throughput; in some cases this can be accomplished while preserving or reducing the implementation area.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
A. Chandrakasan, S. Sheng, R.W. Brodersen, “Design Considerations for a Future Multimedia Terminal”, in Third Generation Wireless Information Network, edited by D. Goodman and S. Nanda, Springer Science+Business Media New York, 1992.
A. Chandrakasan, S. Sheng, R. Brodersen, “Low-power CMOS Digital Design”, IEEE Journal of Solid-state circuit, pp. 473–484, April 1992.
N. Weste and K. Eshragian, Principles of CMOS VLSI Design: A Systems Perspective, Addison-Wesley, MA, 1988.
F. Najm, “Transition Density, A Stochastic Measure of Activities in Digital Circuits”, DAC, pp. 644–649, 1991.
A. Ghosh, S. Devadas, K. Keutzer, J. White, “Estimation of Average Switching Activity in Combinational and Sequential Circuits”, DAC, pp. 253–259, 1992.
A. Chandrakasan, M. Potkonjak, J. Rabaey, R. Brodersen, “An Approach to Power Minimization Using Transformations”, IEEE VLSI Signal Processing Workshop, 1992.
R. W. Brodersen, (ed.), “Anatomy of a Silicon Compiler”, Springer Science+Business Media New York, 1992.
A. Salz, M. Horowitz, “IRSIM: An Incemental MOS Switch-level Simulator”, Proceedings of the 26th ACM/IEEE Design Automation Conference, pp. 173–178, June 1989.
M. Potkonjak and J. Rabaey, “Optimizing the Resource Utilization Using Transformations”, Proc. IEEE ICCAD Conference, Santa Clara, pp. 88–91, November 1991.
J. Rabaey, C. Chu, P. Hoang. M. Potkonjak, “Fast Prototyping of Data Path Intensive Architecture”. IEEE Design and Test, Vol. 8. No. 2, pp. 40–51, 1991.
D. Schultz, “The Influence of Hardware Mapping on High-Level Synthesis”, M.S. report, U.C. Berkeley, 1992.
W.H. Press, B.R Flannery, S.A. Teukolsky, W.T. Vetterling, “Numerical Recipes in C”, Cambridge University Press, 1988.
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2003 Springer Science+Business Media New York
About this chapter
Cite this chapter
Chandrakasan, A.P., Potkonjak, M., Rabaey, J., Brodersen, R.W. (2003). HYPER-LP: A System for Power Minimization Using Architectural Transformations. In: Kuehlmann, A. (eds) The Best of ICCAD. Springer, Boston, MA. https://doi.org/10.1007/978-1-4615-0292-0_10
Download citation
DOI: https://doi.org/10.1007/978-1-4615-0292-0_10
Publisher Name: Springer, Boston, MA
Print ISBN: 978-1-4613-5007-1
Online ISBN: 978-1-4615-0292-0
eBook Packages: Springer Book Archive