Abstract
Once a legacy data block has gone through the flow to allow it be available for new SOC design, it has to be setup properly for use. As is obvious at this point in the book, the nine step flow is not a quick one. A great deal of automation can be incorporated to reduce the manpower associated with the tasks, but the sheer quantity of data that is required to be created is the gating factor. In the maximally automated flow, the machine time for simulation, creation, and validation is about a factor of 10 longer than the operator time manning those steps.
This is a preview of subscription content, log in via an institution.
Buying options
Tax calculation will be finalised at checkout
Purchases are for personal use only
Learn about institutional subscriptionsPreview
Unable to display preview. Download preview PDF.
Author information
Authors and Affiliations
Rights and permissions
Copyright information
© 2003 Springer Science+Business Media New York
About this chapter
Cite this chapter
Chatterjee, P. (2003). Full Chip Verification. In: Legacy Data: A Structured Methodology for Device Migration in DSM Technology. Springer, Boston, MA. https://doi.org/10.1007/978-1-4615-0241-8_14
Download citation
DOI: https://doi.org/10.1007/978-1-4615-0241-8_14
Publisher Name: Springer, Boston, MA
Print ISBN: 978-1-4613-4982-2
Online ISBN: 978-1-4615-0241-8
eBook Packages: Springer Book Archive