Abstract
Since the selection of the AES in 2000, many Rijndael algorithm hardware implementations have been carried out with emphasis on achieving either low area or high performance designs. This is evident in the previous chapter. In this chapter, the designs described in chapter 3 are further developed and two novel Rijndael architectures are presented.
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© 2003 Springer Science+Business Media New York
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McLoone, M., McCanny, J.V. (2003). Further Rijndael Algorithm Architectures and Implementations. In: System-on-Chip Architectures and Implementations for Private-Key Data Encryption. Springer, Boston, MA. https://doi.org/10.1007/978-1-4615-0043-8_4
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DOI: https://doi.org/10.1007/978-1-4615-0043-8_4
Publisher Name: Springer, Boston, MA
Print ISBN: 978-1-4613-4897-9
Online ISBN: 978-1-4615-0043-8
eBook Packages: Springer Book Archive