Abstract
The complexity of highly parallel architecture depends on the parallelism, the area of a single SISO decoder, and the apparatus for parallel data transmission. Chapters 2 and 3 have given the guidelines of choosing proper processing schedule and normalization method of the SISO decoder. Thus, the focus of this chapter is on the circuits that interconnect SISO decoders and memory modules. The trivial apparatus is the fully-connected network. It can offer arbitrary one-to-one interconnection patterns.
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Wong, CC., Chang, HC. (2014). Low-Complexity Solution for Highly Parallel Architecture. In: Turbo Decoder Architecture for Beyond-4G Applications. Springer, New York, NY. https://doi.org/10.1007/978-1-4614-8310-6_4
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DOI: https://doi.org/10.1007/978-1-4614-8310-6_4
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