Abstract
Applications’ traffic tends to be bursty and the locations of hot-spot nodes vary with time. This will dramatically aggregate the blocking problem of wormhole-switched Network-on-Chip (NoC). Most of state-of-the-art traffic balancing solutions, which are based on fully adaptive routing algorithms, may introduce large time/space overhead to routers. On the other hand, partially adaptive routing algorithms, which are time/space efficient, are lack of even or sufficient routing adaptiveness. Due to the lack of a practical model to dynamically keep the routing algorithm deadlock free, most of reconfigurable routing algorithms, which could provide on-demand routing adaptiveness for reducing blocking, are off-line solutions. In this chapter, we will discuss the abacus turn model (AbTM). It was proposed to keep the network deadlock-free by dynamically applying forbidden turns. By this way, the AbTM-based routing algorithms are deadlock-free and on-line reconfigurable. In addition to the AbTM, this chapter also includes a brief discussion about the routing reconfiguration techniques. On detecting the congestion, the reconfigurable routing algorithm first decides the new routing rules. Afterwards, the routing reconfiguration algorithm is exploited to transform the routing function from the old one to the new one. A well-designed routing reconfiguration technique could finish the process in a very short time without blocking and dropping packets. Furthermore, this chapter also briefly discusses the possible solutions to implement reconfigurable routing algorithms, such as table-based solution and LBDR-based solution. Finally, the routing performance will be discussed at the end of this chapter.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Notes
- 1.
A packet takes an NW turn when it changes its direction from north to west [21].
- 2.
A column is called odd (respectively, even) column if its coordinate in dimension-x is an odd (respectively, even) number [22].
- 3.
Southwest packets are those whose destination is on the southwest to current node.
- 4.
Note that, in [18], authors defined RR xy as that if RR xy is true thus the packets from input x are not allowed to be routed to output y at the current router. In this chapter, however, to keep compatible with the definition of R xy , we redefine the RR xy as that if RR xy is true thus the packets towards direction x are allowed to change its direction to y, i.e., the current router allows the xy turn. This redefinition does not change the core principles of LBDR e , but notably facilitates the presentation.
References
S. Bell, B. Edwards, J. Amann, R. Conlin, K. Joyce, V. Leung, J. MacKay, M. Reif, L. Bao, J. Brown, M. Mattina, C.-C. Miao, C. Ramey, D. Wentzlaff, W. Anderson, E. Berger, N. Fairbanks, D. Khan, F. Montenegro, J. Stickney, J. Zook, Tile64 – processor: a 64-core soc with mesh interconnect, in Digest of Technical Papers. IEEE International Solid-State Circuits Conference, San Francisco, 2008, pp. 88–598
http://www.intel.com/content/www/us/en/research/intel-labs-single-chip-cloudcomputer.html
S.R. Vangal, J. Howard, G. Ruhl, S. Dighe, H. Wilson, J. Tschanz, D. Finan, A. Singh, T. Jacob, S. Jain, V. Erraguntla, C. Roberts, Y. Hoskote, N. Borkar, S. Borkar, An 80-tile sub-100-w teraflops processor in 65-nm CMOS. IEEE J. Solid-State Circuits 43(1), 29–41 (2008)
W.J. Dally, B. Towles, Principles and Practices of Interconnection Networks (Morgan Kaufmann, San Francisco, 2004)
J. Kim, C. Nicopoulos, D. Park, R. Das, Y. Xie, N. Vijaykrishnan, M.S. Yousif, C.R. Das, A novel dimensionally-decomposed router for on-chip communication in 3D architectures, in Proceedings of the 34th Annual International Symposium on Computer Architecture, ISCA’07, San Diego (ACM, New York, 2007), pp. 138–149
J. Kim, D. Park, T. Theocharides, N. Vijaykrishnan, C.R. Das, A low latency router supporting adaptivity for on-chip interconnects, in Proceedings of Design Automation Conference, San Diego, 2005, pp. 559–564
A. Singh, W.J. Dally, A.K. Gupta, B. Towles, Goal: a load-balanced adaptive routing algorithm for torus networks, in Proceedings of International Symposium on Computer Architecture, San Diego, 2003, pp. 194–205
J.W. van den Brand, C. Ciordas, K. Goossens, T. Basten, Congestion-controlled best-effort communication for Networks-on-Chip, in Design, Automation Test in Europe Conference Exhibition, Nice, 2007, pp. 1–6
J. Duato, I. Johnson, J. Flich, F. Naven, P. Garcia, T. Nachiondo, A new scalable and cost-effective congestion management strategy for lossless multistage interconnection networks, in Proceedings of International Symposium on High-Performance Computer Architecture, San Francisco, 2005, pp. 108–119
P. Gratz, B. Grot, S.W. Keckler, Regional congestion awareness for load balance in Networks-on-Chip, in Proceedings of IEEE International Symposium on High Performance Computer Architecture, Salt Lake City, 2008, pp. 203–214
D. Park, R. Das, C. Nicopoulos, J. Kim, N. Vijaykrishnan, R. Iyer, C.R. Das, Design of a dynamic priority-based fast path architecture for on-chip interconnects, in Proceedings of IEEE Symposium on High-Performance Interconnects, Stanford, 2007, pp. 15–20
W.J. Dally, Virtual-channel flow control. IEEE Trans. Parallel Distrib. Syst. 3(2), 194–205 (1992)
S.A. Felperin, L. Gravano, G.D. Pifarre, J.L.C. Sanz, Fully-adaptive routing: packet switching performance and wormhole algorithms, in Proceedings of ACM/IEEE Conference on Supercomputing, Albuquerque, 1991, pp. 654–663
W.J. Dally, H. Aoki, Deadlock-free adaptive routing in multicomputer networks using virtual channels. IEEE Trans. Parallel Distrib. Syst. 4(4), 466–475 (1993)
J. Duato, A new theory of deadlock-free adaptive routing in wormhole networks. IEEE Trans. Parallel Distrib. Syst. 4(12), 1320–1331 (1993)
Y.M. Boura, C.R. Das, Efficient fully adaptive wormhole routing in n-dimensional meshes, in Proceedings of International Conference on Distributed Computing Systems, Poznan, 1994, pp. 589–596
J.H. Upadhyay, V. Varavithya, P. Mohapatra, Efficient and balanced adaptive routing in two-dimensional meshes, in Proceedings of IEEE Symposium on High-Performance Computer Architecture, Raleigh, 1995, pp. 112–121
J. Flich, S. Rodrigo, J. Duato, An efficient implementation of distributed routing algorithms for NoCs, in Proceedings of ACM/IEEE International Symposium on Networks-on-Chip, Newcastle, 2008, pp. 87–96
L.-S. Peh, W.J. Dally, A delay model and speculative architecture for pipelined routers, in Proceedings of International Symposium on High-Performance Computer Architecture, Nuevo Leone, 2001, pp. 255–266
S. Ma, N.E. Jerger, Z. Wang, Whole packet forwarding: efficient design of fully adaptive routing algorithms for Networks-on-Chip, in Proceedings of the 2012 IEEE 18th International Symposium on High-Performance Computer Architecture, HPCA’12, New Orleans (IEEE Computer Society, Washington, DC, 2012), pp. 1–12
C.J. Glass, L.M. Ni, The turn model for adaptive routing, in Proceedings of International Symposium on Computer Architecture, Gold Coast, 1992, pp. 278–287
G.M. Chiu, The odd-even turn model for adaptive routing. IEEE Trans. Parallel Distrib. Syst. 11(7), 729–738 (2000)
N. Barrow-Williams, C. Fensch, S. Moore, A communication characterisation of splash-2 and parsec, in IEEE International Symposium on Workload Characterization, Austin, 2009, pp. 86–97
L.M. Ni, P.K. McKinley, A survey of wormhole routing techniques in direct networks. Computer 26(2), 62–76 (1993)
T.L. Rodeheffer, M.D. Schroeder, Automatic reconfiguration in autonet, in Proceedings of ACM Symposium on Operating Systems Principles, Pacific Grove, 1991, pp. 183–197
O. Lysne, J.M. Montanana, J. Flich, J. Duato, T.M. Pinkston, T. Skeie, An efficient and deadlock-free network reconfiguration protocol. IEEE Trans. Comput. 57(6), 762–779 (2008)
O. Lysne, J. Duato, Fast dynamic reconfiguration in irregular networks, in Proceedings of International Conference on Parallel Processing, Toronto, 2000, pp. 449–458
R. Casado, A. Bermudez, J. Duato, F.J. Quiles, J.L. Sanchez, A protocol for deadlock-free dynamic reconfiguration in high-speed local area networks. IEEE Trans. Parallel Distrib. Syst. 12(2), 115–132 (2001)
D. Avresky, N. Natchev, Dynamic reconfiguration in computer clusters with irregular topologies in the presence of multiple node and link failures. IEEE Trans. Comput. 54(5), 603–615 (2005)
R. Casado, A. Bermudez, F.J. Quiles, J.L. Sanchez, J. Duato, Performance evaluation of dynamic reconfiguration in high-speed local area networks, in Proceedings of International Symposium on High-Performance Computer Architecture, Toulouse, 2000, pp. 85–96
J. Wu, A fault-tolerant and deadlock-free routing protocol in 2D meshes based on odd-even turn model. IEEE Trans. Comput. 52(9), 1154–1169 (2003)
Z. Zhang, A. Greiner, S. Taktak, A reconfigurable routing algorithm for a fault-tolerant 2D-mesh Network-on-Chip, in Proceedings of ACM/IEEE Design Automation Conference, Anaheim, 2008, pp. 441–446
D. Fick, A. DeOrio, G. Chen, V. Bertacco, D. Sylvester, D. Blaauw, A highly resilient routing algorithm for fault-tolerant NoCs, in Proceedings of Design, Automation Test in Europe Conference Exhibition, Nice, 2009, pp. 21–26
B. Fu, Y. Han, H. Li, X. Li, A new multiple-round dimension-order routing for Networks-on-Chip. IEICE Trans. Inf. Syst. E94-D, 809–821 (2011)
B. Fu, Y. Han, H. Li, X. Li, Zonedefense: a fault-tolerant routing for 2-d meshes without virtual channels. IEEE Trans. Very Large Scale Integr. Syst. (2013)
L. Zhang, Y. Han, Q. Xu, X. Li, Defect tolerance in homogeneous manycore processors using core-level redundancy with unified topology, in Design, Automation and Test in Europe, DATE’08, Munich, 2008, pp. 891–896
L. Zhang, Y. Han, Q. Xu, X. Li, H. Li, On topology reconfiguration for defect-tolerant noc-based homogeneous manycore systems. IEEE Trans. Very Large Scale Integr. Syst. 17(9), 1173–1186 (2009)
W.J. Dally, C.L. Seitz, Deadlock-free message routing in multiprocessor interconnection networks. IEEE Trans. Comput. C-36(5), 547–553 (1987)
A. Mejia, J. Flich, J. Duato, S.-A. Reinemo, T. Skeie, Segment-based routing: an efficient fault-tolerant routing algorithm for meshes and tori, in Proceedings of International Symposium on Parallel and Distributed Processing, Rhodes Island, 2006, p. 10
M. Palesi, R. Holsmark, S. Kumar, V. Catania, Application specific routing algorithms for Networks-on-Chip. IEEE Trans. Parallel Distrib. Syst. 20(3), 316–330 (2009)
M.A. Kinsy, M.H. Cho, T. Wen, E. Suh, M. van Dijk, S. Devadas, Application-aware deadlock-free oblivious routing, in Proceedings of International Symposium on Computer Architecture, Austin (ACM, New York, 2009), pp. 208–219
J. Cong, C. Liu, G. Reinman, Aces: application-specific cycle elimination and splitting for deadlock-free routing on irregular Network-on-Chip, in Proceedings of ACM/IEEE Design Automation Conference, Anaheim, 2010, pp. 443–448
B. Fu, Y. Han, J. Ma, H. Li, X. Li, An abacus turn model for time/space-efficient reconfigurable routing, in Proceedings of the 38th Annual International Symposium on Computer Architecture, ISCA’11, San Jose (ACM, New York, 2011), pp. 259–270
Y. Han, Y. Hu, X. Li, H. Li, A. Chandra, Embedded test decompressor to reduce the required channels and vector memory of tester for complex processor circuit. IEEE Trans. Very Large Scale Integr. Syst. 15(5), 531–540 (2007)
A. Singh, W.J. Dally, A.K. Gupta, B. Towles, Adaptive channel queue routing on k-ary n-cubes, in Proceedings of ACM Symposium on Parallelism in Algorithms and Architectures, Barcelona, 2004, pp. 11–19
D. Seo, A. Ali, W.-T. Lim, N. Rafique, M. Thottethodi, Near-optimal worst-case throughput routing for two-dimensional mesh networks, in Proceedings of International Symposium on Computer Architecture, Madison, 2005, pp. 432–443
M.M.K. Martin, D.J. Sorin, B.M. Beckmann, M.R. Marty, M. Xu, A.R. Alameldeen, K.E. Moore, M.D. Hill, D.A. Wood, Multifacet’s general execution-driven multiprocessor simulator (GEMS) toolset. ACM SIGARCH Comput. Archit. News 33(4), 92–99 (2005)
S.C. Woo, M. Ohara, E. Torrie, J.P. Singh, A. Gupta, The splash-2 programs: characterization and methodological considerations, in Proceedings of International Symposium on Computer Architecture, Santa Margherita Ligure, 1995, pp. 24–36
C. Bienia, S. Kumar, J.P. Singh, K. Li, The parsec benchmark suite: characterization and architectural implications, in Proceedings of International Conference on Parallel Architectures and Compilation Techniques, PACT’08, Toronto (ACM, New York, 2008), pp. 72–81
E.S. Shin, V.J. Mooney III, G.F. Riley, Round-robin arbiter design and generation, in Proceedings of International Symposium on System Synthesis, Kyoto, 2002, pp. 243–248
A.B. Kahng, B. Lin, K. Samadi, R.S. Ramanujam, Trace-driven optimization of Networks-on-Chip configurations, in Proceedings of ACM/IEEE Design Automation Conference (DAC), Anaheim, 2010, pp. 437–442
S. Rodrigo, J. Flich, A. Roca, S. Medardoni, D. Bertozzi, J. Camacho, F. Silla, J. Duato, Addressing manufacturing challenges with cost-efficient fault tolerant routing, in Proceedings of International Symposium on Networks-on-Chip, Grenoble, 2010, pp. 25–32
Author information
Authors and Affiliations
Corresponding author
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2014 Springer Science+Business Media New York
About this chapter
Cite this chapter
Fu, B., Han, Y., Li, H., Li, X. (2014). The Abacus Turn Model. In: Palesi, M., Daneshtalab, M. (eds) Routing Algorithms in Networks-on-Chip. Springer, New York, NY. https://doi.org/10.1007/978-1-4614-8274-1_4
Download citation
DOI: https://doi.org/10.1007/978-1-4614-8274-1_4
Published:
Publisher Name: Springer, New York, NY
Print ISBN: 978-1-4614-8273-4
Online ISBN: 978-1-4614-8274-1
eBook Packages: EngineeringEngineering (R0)