Skip to main content

Scalable Architecture for All-Optical Wavelength-Routed Networks-on-Chip

  • Chapter
  • First Online:
  • 2027 Accesses

Abstract

Scaling the transistor feature size along with the increase of chip operation frequency leads to the growth of circuit complexity, which makes the design of electrical interconnects increasingly difficult in large chips. Optics provides low power dissipation which remains independent of capacity and distance, as well as wavelength parallelism, ultra-high throughput, and minimal access latencies. Additionally, wavelength routing, bit rate transparency, high-capacity, low propagation loss, and low power dissipation of silicon photonics are attractive for realizing optical Networks-on-Chip (ONoC) in Chip Multi-Processors (CMPs). In this chapter, we propose a new architecture for nanophotonic NoC, named 2D-HERT, which consists of optical data and control planes. The proposed data plane is built upon a new topology and all-optical switches that passively route optical data streams based on their wavelengths. Utilizing wavelength routing method, the proposed deterministic routing algorithm, and Wavelength Division Multiplexing (WDM) technique, the proposed data plane eliminates the need for optical resource reservation at the intermediate nodes. For resolving end-point contention, we propose an all-optical request-grant arbitration architecture which reduces optical losses compared to the alternative arbitration schemes. By performing a series of simulations, we study the efficiency of the proposed architecture, its power and energy consumption, and the data transmission delay.

This is a preview of subscription content, log in via an institution.

Buying options

Chapter
USD   29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD   129.00
Price excludes VAT (USA)
  • Available as EPUB and PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD   169.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info
Hardcover Book
USD   169.99
Price excludes VAT (USA)
  • Durable hardcover edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Learn about institutional subscriptions

References

  1. L. Benini, G. De Micheli, Networks on chips: A new SoC paradigm. IEEE Comp. 35(1), 70–80 (2002)

    Article  Google Scholar 

  2. A. Shacham, K. Bergman, L.P. Carloni, Maximizing GFLOPS-per-Watt: High-bandwidth, low power photonic on-chip networks, in P = ac 2 Conference (New York, 2006), pp. 12–21

    Google Scholar 

  3. K.C. Saraswat, F. Mohammadi, Effect of scaling of interconnections on the time delay of VLSI circuits. IEEE Trans. Electron. Dev. ED-29, 645–650 (1982)

    Article  Google Scholar 

  4. D. Miller, Rationale and challenges for optical interconnects to electronic chips. Proc. IEEE. 88(6), 728–749 (2000)

    Google Scholar 

  5. A. Shacham, K. Bergman, L.P. Carloni, Photonic networks-on-chip for future generations of chip multi-processors. IEEE Trans. Comput. 57, 1–15 (2008)

    Article  MathSciNet  Google Scholar 

  6. F. Adam, R. Gutiérrez-Castrejón, I. Tomkos, B. Hallock, R. Vodhanel, A. Coombe, W. Yuen, R. Moreland, B. Garrett, C. Duvall, C. Chang-Hasnain, Transmission performance of a 1.5-μm 2.5-Gb/s directly modulated tunable VCSEL. Photonics Technol. Lett. 15(4), 599–601 (2003)

    Article  Google Scholar 

  7. C. Guillemot, M. Renaud, P. Gambini, C. Janz, I. Andonovic, R. Bauknecht, B. Bostica, M. Burzio, F. Callegati, M. Casoni, D. Chiaroni, F. Clerot, S.L. Danielsen, F. Dorgeuille, A. Dupas, A. Franzen, P.B. Hansen, D.K. Hunter, A. Kloch, R. Krahenbuhl, B. Lavigne, A. Le Corre, C. Raffaelli, M. Schilling, J.-C. Simon, L. Zucchelli, Transparent optical packet switching: The European ACTS KEOPS project approach. J. Lightwave Technol. 16(12), 2117–2134 (1998)

    Article  Google Scholar 

  8. N. Kirman, M. Kirman, R.K. Dokania, J.F. Martinez, A.B. Apsel, M.A. Watkins, D.H. Albonesi, Leveraging optical technology in future bus-based chip multiprocessors, in IEEE/ACM Annual International Symposium on Microarchitecture (Florida, USA, 2006), pp. 492–503

    Google Scholar 

  9. Y. Pan, P. Kumar, J. Kim, G. Memik, Y. Zhang, A. Choudhary, Firefly: Illuminating future network-on-chip with nanophotonics, in International Symposium on Computer Architecture (ISCA) (Austin, Texas, USA, 2009), pp. 429–440

    Google Scholar 

  10. D. Vantrease, R. Schreiber, M. Monchiero, M. McLaren, N.P. Jouppi, M. Fiorentino, A. Davis, N.L. Binkert, R.G. Beausoleil, J.H. Ahn, Corona: System implications of emerging nanophotonic technology, in International Symposium on Computer Architecture (ISCA) (Beijing, China, 2008), pp. 153–164

    Google Scholar 

  11. S. Koohi, S. Hessabi, Contention-free on-chip routing of optical packets, in International Symposium on Networks-on-Chip (NOCS) (San Diego, CA, USA, 2009), pp. 134–143

    Google Scholar 

  12. M.J. Cianchetti, J.C. Kerekes, D.H. Albonesi, Phastlane: A rapid transit optical routing network, in International Symposium on Computer Architecture (ISCA) (Austin, Texas, USA, 2009), pp. 441–450

    Google Scholar 

  13. H. Gu, K.H. Mo, J. Xu, W. Zhang, A Low-power Low-cost optical router for optical networks-on-chip in multiprocessor systems-on-chip, in IEEE Symposium on VLSI (Kyoto, Japan, 2009), pp. 19–24

    Google Scholar 

  14. M. Briere, B. Girodias, Y. Bouchebaba, G. Nicolescu, F. Mieyeville, F. Gaffiot, I. O’Connor, System level assessment of an optical NoC in an MPSoC platform, in Design, Automation and Test in Europe (DATE) (Nice, France, 2007), pp. 1084–1089

    Google Scholar 

  15. H. Gu, J. Xu, W. Zhang, A low-power fat tree-based optical network-on-chip for multiprocessor system-on-chip, in Design, Automation and Test in Europe (DATE) (Nice, France, 2009), pp. 3–8

    Google Scholar 

  16. H. Gu, J. Xu, Z. Wang, A novel optical mesh network-on-chip for gigascale systems-on-chip, in Asia Pacific Conference on Circuits and Systems (APCCAS) (Macao, China, 2008), pp. 1728–1731

    Google Scholar 

  17. I. Stojmenovic, Honeycomb networks: Topological properties and communication algorithms. IEEE Trans. Parall. Distr. Syst. 8(10), 1036–1042 (1997)

    Article  Google Scholar 

  18. A. Joshi, C. Batten, Y.-J. Kwon, S. Beamer, I. Shamim, K. Asanovic, V. Stojanovi, Silicon-photonic clos networks for global on-chip communication, in International Symposium on Networks-on-Chip (NOCS) (San Diego, CA, USA, 2009), pp. 124–133

    Google Scholar 

  19. F. Xu, A.W. Poon, Multimode-interference waveguide crossing coupled microring-resonator-based switch nodes for photonic networks-on-chip, in Lasers and Electro-Optics Conference and Quantum Electronics and Laser Science (CLEO/QELS) Conference (San Jose, CA, 2008), pp. 1–2

    Google Scholar 

  20. N. Sherwood-Droz, H. Wang, L. Chen, B.G. Lee, A. Biberman, K. Bergman, M. Lipson, Optical 4×4 hitless silicon router for optical networks-on-chip (NoC). Opt. Express 16(20), 15915–15922 (2008)

    Article  Google Scholar 

  21. P. Koonath, T. Indukuri, B. Jalali, Add-drop filters utilizing vertically coupled microdisk resonators in silicon. J. Appl. Phys. Lett. 86, 091102-1–091102-3 (2005)

    Article  Google Scholar 

  22. B.A. Small, B.G. Lee, K. Bergman, Q. Xu, M. Lipson, Multiple-wavelength integrated photonic networks based on microring resonator devices. J. Opt. Netw. 6(2), 112–120 (2007)

    Article  Google Scholar 

  23. S. Koohi, S. Hessabi, All-optical wavelength-routed NoC based on a novel hierarchical topology, in International Symposium on Networks-on-Chip (NOCS) (Pittsburgh, Pennsylvania, USA, 2011), pp. 97–104

    Google Scholar 

  24. OMNeT++ discrete event simulation system, Available online at http://www.omnetpp.org/

  25. ITRS, The international technology roadmap for semiconductors – 2009 edition, (2009), Available at http://public.itrs.net

  26. S. Koohi, M.M. Aghatabar, S. Hessabi, Evaluation of traffic pattern effect on power consumption in mesh and torus-based network-on-chips, in International Symposium on Integrated Circuits (ISIC), (Orchard Hot, Singapore, 2007)

    Google Scholar 

  27. S. Manipatruni, Q. Xu, M. Lipson, PINIP based high-speed high-extinction ratio micron-size silicon electrooptic modulator. Opt. Express 15(20), 13035–13042 (2007)

    Article  Google Scholar 

  28. I. O’Connor, F. Gaffiot, On-chip optical interconnect for low-power, in Ultra-Low Power Electronics and Design, ed. by E. Macii (Kluwer, Dordrecht, 2004)

    Google Scholar 

  29. G. Chen, H. Chen, M. Haurylau, N. Nelson, P.M. Fauchet, E.G. Friedman, D.H. Albonesi, Predictions of CMOS compatible on-chip optical interconnect. VLSI J. Integr. 40(4), 434–446 (2007)

    Article  Google Scholar 

  30. M. Lipson, Guiding, modulating, and emitting light on silicon-challenges and opportunities. J. Lightwave Technol. 23(12), 4222 (2005)

    Article  Google Scholar 

  31. D.M. Vantrease, Optical tokens in many-core processors, University of Wisconsin (2010)

    Google Scholar 

  32. M. Haurylau, C.Q. Chen, H. Chen, J.D. Zhang, N.A. Nelson, D.H. Albonesi, E.G. Friedman, P.M. Fauchet, On-chip optical interconnect roadmap: Challenges and critical directions. IEEE J. Sel. Top. Quant. Electron. 12(6), 1699–1705 (2006)

    Article  Google Scholar 

  33. K. Greene, A record-breaking optical chip, MIT Technol. Rev. Available online at http://www.technologyreview.com/Infotech/21005/?a = f

  34. L. Wosinski, W. Zhechao, Integrated silicon nanophotonics: A solution for computer interconnects, in IEEE International Conference on Transparent Optical Networks (ICTON) (Stockholm, Sweden, 2011), pp. 1–4

    Google Scholar 

  35. ITU-T Technology Watch Report, The optical world, June 2011, Available online at http://www.itu.int/ITU-T/techwatch

  36. K. Bourzac, Laser-Quick Data Transfer, MIT Technol. Rev. Available online at http://www.technologyreview.com/computing/32324/

  37. B. Black, M. Annavaram, N. Brekelbaum, J. DeVale, L. Jiang, G. Loh, D. McCaule, P. Morrow, D. Nelson, D. Pantuso, P. Reed, J. Rupley, S. Shankar, J. Shen, C. Webb, Die stacking (3D) microarchitecture, in IEEE/ACM International Symposium on Micro-architecture (Florida, USA, 2006), pp. 469–479

    Google Scholar 

  38. C. Batten, A. Joshi, J. Orcutt, A. Khilo, B. Moss, C. Holzwarth,M. Popovic, H. Li, H. Smith, J. Hoyt, F. Kartner, R. Ram, V. Stojanovic, K. Asanovic, Building manycore processor-to-dram networks with monolithic silicon photonics, in IEEE/ACM International Symposium on Micro-architecture (New York, USA, 2009), pp. 8–21

    Google Scholar 

  39. Q. Xu, D. Fattal, R. Beausoleil, Silicon microring resonators with 1.5 μm radius. Opt. Express.16(6), 4309–4315 (2008)

    Google Scholar 

  40. B. Guha, B. Kyotoku, M. Lipson, CMOS-compatible athermal silicon microring resonators. Opt. Express 18, 3487–3493 (2010)

    Article  Google Scholar 

  41. J. Ahn, M. Fiorentino, R.G. Beausoleil, N. Binkert, A. Davis, D. Fattal, N.P. Jouppi, M. McLaren, C.M. Santori, R.S. Schreiber, S.M. Spillane, D. Vantrease, Q. Xu, Devices and architectures for photonic chip-scale integration. Appl. Phys. Mater. Sci. Process. 95(4), 989–997 (2009)

    Article  Google Scholar 

  42. C. Nitta, M. Farrens, V. Akella, Addressing system-level trimming issues in on-chip nanophotonic networks, in IEEE International Symposium on High Performance Computer Architecture (HPCA) (San Antonio, Texas, USA, 2011), pp. 122–131

    Google Scholar 

  43. Y. Pan, J. Kim, G. Memik. Flexishare, Channel sharing for an energy-efficient nanophotonic crossbar, in IEEE International Symposium on High Performance Computer Architecture (HPCA) (Bangalore, India, 2010), pp. 1–12

    Google Scholar 

Download references

Author information

Authors and Affiliations

Authors

Corresponding author

Correspondence to Somayyeh Koohi .

Editor information

Editors and Affiliations

Rights and permissions

Reprints and permissions

Copyright information

© 2014 Springer Science+Business Media New York

About this chapter

Cite this chapter

Koohi, S., Hessabi, S. (2014). Scalable Architecture for All-Optical Wavelength-Routed Networks-on-Chip. In: Palesi, M., Daneshtalab, M. (eds) Routing Algorithms in Networks-on-Chip. Springer, New York, NY. https://doi.org/10.1007/978-1-4614-8274-1_13

Download citation

  • DOI: https://doi.org/10.1007/978-1-4614-8274-1_13

  • Published:

  • Publisher Name: Springer, New York, NY

  • Print ISBN: 978-1-4614-8273-4

  • Online ISBN: 978-1-4614-8274-1

  • eBook Packages: EngineeringEngineering (R0)

Publish with us

Policies and ethics