Abstract
Scaling the transistor feature size along with the increase of chip operation frequency leads to the growth of circuit complexity, which makes the design of electrical interconnects increasingly difficult in large chips. Optics provides low power dissipation which remains independent of capacity and distance, as well as wavelength parallelism, ultra-high throughput, and minimal access latencies. Additionally, wavelength routing, bit rate transparency, high-capacity, low propagation loss, and low power dissipation of silicon photonics are attractive for realizing optical Networks-on-Chip (ONoC) in Chip Multi-Processors (CMPs). In this chapter, we propose a new architecture for nanophotonic NoC, named 2D-HERT, which consists of optical data and control planes. The proposed data plane is built upon a new topology and all-optical switches that passively route optical data streams based on their wavelengths. Utilizing wavelength routing method, the proposed deterministic routing algorithm, and Wavelength Division Multiplexing (WDM) technique, the proposed data plane eliminates the need for optical resource reservation at the intermediate nodes. For resolving end-point contention, we propose an all-optical request-grant arbitration architecture which reduces optical losses compared to the alternative arbitration schemes. By performing a series of simulations, we study the efficiency of the proposed architecture, its power and energy consumption, and the data transmission delay.
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Koohi, S., Hessabi, S. (2014). Scalable Architecture for All-Optical Wavelength-Routed Networks-on-Chip. In: Palesi, M., Daneshtalab, M. (eds) Routing Algorithms in Networks-on-Chip. Springer, New York, NY. https://doi.org/10.1007/978-1-4614-8274-1_13
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DOI: https://doi.org/10.1007/978-1-4614-8274-1_13
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