Skip to main content

Basic Concepts on On-Chip Networks

  • Chapter
  • First Online:
Routing Algorithms in Networks-on-Chip

Abstract

As the number of cores integrated into a System-on-Chip increases, the role played by the communication system becomes more and more important. The Network-on-Chip design paradigm is today recognised as the most viable communication infrastructure to deal with the scalability issues which characterise the ultra-deep sub-micron silicon era. In this chapter, some of the most important concepts in the context of on-chip networks will be reviewed. Basic concepts including, network topologies, switching techniques, and routing algorithms will be recalled. Such topics represent the conceptual bases exploited by the strategies, the mechanisms, and the methodologies discussed in the subsequent chapters.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD 129.00
Price excludes VAT (USA)
  • Available as EPUB and PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD 169.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info
Hardcover Book
USD 169.99
Price excludes VAT (USA)
  • Durable hardcover edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

References

  1. G. Ascia, V. Catania, M. Palesi, D. Patti, Implementation and analysis of a new selection strategy for adaptive routing in networks-on-chip. IEEE Trans. Comput. 57(6), 809–820 (2008)

    Article  MathSciNet  Google Scholar 

  2. L. Benini, G.D. Micheli, Networks on chips: a new SoC paradigm. IEEE Comput. 35(1), 70–78 (2002)

    Article  Google Scholar 

  3. D.P. Bertsekas, R.G. Gallager, Data Networks (Prentice Hall, Englewood Cliffs, 1992)

    MATH  Google Scholar 

  4. C.-H. Chao, K.-Y. Jheng, H.-Y. Wang, J.-C. Wu, A.-Y. Wu, Traffic- and thermal-aware run-time thermal management scheme for 3D NoC systems, in ACM/IEEE International Symposium on Networks-on-Chip, Grenoble, 2010, pp. 223–230

    Google Scholar 

  5. A.A. Chien, J.H. Kim, Planar-adaptive routing: low-cost adaptive networks for multiprocessors. J. ACM 42(1), 91–123 (1995)

    Article  MATH  Google Scholar 

  6. G.-M. Chiu, The odd-even turn model for adaptive routing. IEEE Trans. Parallel Distrib. Syst. 11(7), 729–738 (2000)

    Article  Google Scholar 

  7. W.J. Dally, C. Seitz, Deadlock-free message routing in multiprocessor interconnection networks. IEEE Trans. Comput. C(36), 547–553 (1987)

    Google Scholar 

  8. W.J. Dally, B. Towles, Route packets, not wires: on-chip interconnection networks, in ACM/IEEE Design Automation Conference, Las Vegas, 2001, pp. 684–689

    Google Scholar 

  9. W.J. Dally, B. Towles, Principles and Practices of Interconnection Networks (Morgan Kaufmann, San Francisco, 2004)

    Google Scholar 

  10. M. Daneshtalab, M. Ebrahimi, T.C. Xu, P. Liljeberg, H. Tenhunen, A generic adaptive path-based routing method for MPSoCs. Elsevier J. Syst. Archit. 57(1), 109–120 (2011)

    Article  Google Scholar 

  11. M.M. de Azevedo, D. Blough, Fault-tolerant clock synchronization of large multicomputers via multistep interactive convergence, in International Conference on Distributed Computing Systems, Hong Kong, 1996, pp. 249–257

    Google Scholar 

  12. J. Duato, A new theory of deadlock-free adaptive routing in wormhole networks. IEEE Trans. Parallel Distrib. Syst. 4(12), 1320–1331 (1993)

    Article  Google Scholar 

  13. J. Duato, A necessary and sufficient condition for deadlock-free routing in wormhole networks. IEEE Trans. Parallel Distrib. Syst. 6(10), 1055–1067 (1995)

    Article  Google Scholar 

  14. J. Duato, S. Yalamanchili, L. Ni, Interconnection Networks: An Engineering Approach (Morgan Kaufmann, San Francisco, 2002)

    Google Scholar 

  15. M. Ebrahimi, M. Daneshtalab, F. Fahimeh, P. Liljeberg, J. Plosila, M. Palesi, H. Tenhunen, HARAQ: congestion-aware learning model for highly adaptive routing algorithm in on-chip networks, in ACM/IEEE International Symposium on Networks-on-Chip, Copenhagen, May 2012, pp. 19–26

    Google Scholar 

  16. M. Ebrahimi, M. Daneshtalab, P. Liljeberg, J. Plosila, J. Flich, H. Tenhunen, Path-based partitioning methods for 3d networks-on-chip with minimal adaptive routing. IEEE Trans. Comput. 99, pp. 1, doi: 10.1109/TC.2012.255

    Google Scholar 

  17. M. Ebrahimi, M. Daneshtalab, P. Liljeberg, J. Plosila, H. Tenhunen, Cluster-based topologies for 3D networks-on-chip using advanced inter-layer bus architecture. Elsevier J. Comput. Syst. Sci. 79(4), 475–491 (2013)

    Article  MathSciNet  MATH  Google Scholar 

  18. C.J. Glass, L.M. Ni, The turn model for adaptive routing. J. Assoc. Comput. Mach. 41(5), 874–902 (1994)

    Article  Google Scholar 

  19. J. Hu, R. Marculescu, DyAD – smart routing for networks-on-chip, in ACM/IEEE Design Automation Conference, San Diego, 7–11 June 2004, pp. 260–263

    Google Scholar 

  20. ITRS 2011 edition, International Technology Roadmap for Semiconductors (2011). http://www.itrs.net/

  21. A. Jantsch, H. Tenhunen (eds.), Networks on Chip, chapter 1 (Kluwer Academic, Boston, 2003)

  22. S. Kumar, A. Jantsch, J.-P. Soininen, M. Forsell, M. Millberg, J. Oberg, K. Tiensyrja, A. Hemani, A network on chip architecture and design methodology, in IEEE Computer Society Annual Symposium on VLSI, Pittsburg, p. 117, 2002

    Google Scholar 

  23. K. Li, R. Schaefer, A hypercube shared virtual memory, in International Conference on Parallel Processing, University Park, 1989, pp. 125–132

    Google Scholar 

  24. X. Lin, L.M. Ni, Multicast communication in multicomputer networks. IEEE Trans. Parallel Distrib. Syst. 4, 1105–1117 (1993)

    Article  Google Scholar 

  25. P.K. McKinley, H. Xu, E.T. Kalns, L.M. Ni, CompaSS: efficient communication services for scalable architectures, in International Conference on Supercomputing, Washington, D.C., 1992, pp. 478–487

    Google Scholar 

  26. G.D. Micheli, L. Benini, Powering networks on chips: energy-efficient and reliable interconnect design for SoCs, in International IEEE Symposium on Systems Synthesis, Montréal, 2001, pp. 33–38

    Google Scholar 

  27. P. Mohapatra, Wormhole routing techniques for directly connected multicomputer systems. ACM Comput. Surv. 30(8), 374–410 (1998)

    Article  Google Scholar 

  28. L.M. Ni, P.K. McKinley, A survey of wormhole routing techniques in direct networks. IEEE Comput. 26, 62–76 (1993)

    Article  Google Scholar 

  29. E. Nilsson, M. Millberg, J. Oberg, A. Jantsch, Load distribution with the proximity congestion awareness in a network on chip, in Design, Automation and Test in Europe, Washington, D.C., 2003, pp. 1126–1127

    Google Scholar 

  30. M. Palesi, R. Holsmark, S. Kumar, V. Catania, Application specific routing algorithms for networks on chip. IEEE Trans. Parallel Distrib. Syst. 20(3), 316–330 (2009)

    Article  Google Scholar 

  31. D. Park, S. Eachempati, R. Das, A. Mishra, Y. Xie, N. Vijaykrishnan, C.R. Das, MIRA: a multi-layered on-chip interconnect router architecture, in International Symposium on Computer Architecture, Beijing, 2008, pp. 251–261

    Google Scholar 

  32. J. Upadhyay, V. Varavithya, P. Mohapatra, A traffic-balanced adaptive wormhole routing scheme for two-dimensional meshes. IEEE Trans. Comput. 46(2), 190–197 (1997)

    Article  Google Scholar 

  33. H. Xu, P.K. McKinley, E.T. Kalns, L.M. Ni, Efficient implementation of barrier synchronization in wormhole-routed hypercube multicomputers. J. Parallel Distrib. Comput. 16, 172–184 (1992)

    Article  Google Scholar 

  34. T.T. Ye, L. Benini, G.D. Micheli, Packetization and routing analysis of on-chip multiprocessor networks. J. Syst. Archit. 50(2–3), 81–104 (2004)

    Article  Google Scholar 

Download references

Author information

Authors and Affiliations

Authors

Corresponding author

Correspondence to Masoud Danashtalab .

Editor information

Editors and Affiliations

Rights and permissions

Reprints and permissions

Copyright information

© 2014 Springer Science+Business Media New York

About this chapter

Cite this chapter

Danashtalab, M., Palesi, M. (2014). Basic Concepts on On-Chip Networks. In: Palesi, M., Daneshtalab, M. (eds) Routing Algorithms in Networks-on-Chip. Springer, New York, NY. https://doi.org/10.1007/978-1-4614-8274-1_1

Download citation

  • DOI: https://doi.org/10.1007/978-1-4614-8274-1_1

  • Published:

  • Publisher Name: Springer, New York, NY

  • Print ISBN: 978-1-4614-8273-4

  • Online ISBN: 978-1-4614-8274-1

  • eBook Packages: EngineeringEngineering (R0)

Publish with us

Policies and ethics