Turbo Codes

Chapter

Abstract

A major step towards the Shannon limit was done in 1993 by introducing the so called turbo code (TC).

Keywords

Convolution 

References

  1. 1.
    Berrou, C., Glavieux, A., Thitimajshima, P.: Near Shannon limit error-correcting coding and decoding: turbo-codes. In: Proceedings of 1993 International Conference on Communications (ICC ’93), pp. 1064–1070, Geneva, Switzerland (1993)Google Scholar
  2. 2.
    ten Brink, S.: Convergence behavior of iteratively decoded parallel concatenated codes. IEEE Trans. Commun. 49(10), 1727–1737 (2001). doi: 10.1109/26.957394 Google Scholar
  3. 3.
    ten Brink, S., Kramer, G., Ashikhmin, A.: Design of low-density parity-check codes for modulation and detection. IEEE Trans. Commun. 52(4), 670–678 (2004). doi: 10.1109/TCOMM.2004.826370 Google Scholar
  4. 4.
    May, M.: Dissertation in preparation: Architectures for High-throughput and Reliable Iterative Channel Decoders. Ph.D. Thesis, Department of Electrical Engineering and Information Technology, University of Kaiserslautern (2012)Google Scholar
  5. 5.
    Vogt, J., Finger, A.: Improving the Max-Log-MAP turbo decoder. IEEE Electron. Lett. 36, 1937–1939 (2000)CrossRefGoogle Scholar
  6. 6.
    Michel, H., Wehn, N.: Turbo-decoder quantization for UMTS. IEEE Commun. Lett. 5(2), 55–57 (2001)CrossRefGoogle Scholar
  7. 7.
    Wu, Y., Woerner, B.D.: The influence of quantization and fixed point arithmetic upon the BER performance of turbo codes. In: Proceedings of 1999 International Conference on Vehicular Technology (VTC ’99), pp. 1683–1687 (1999)Google Scholar
  8. 8.
    Worm, A., Hoeher, P., Wehn, N.: Turbo-decoding without SNR estimation. IEEE Commun. Lett. 4(6), 193–195 (2000)CrossRefGoogle Scholar
  9. 9.
    Vogt, T.: A Reconfigurable Application-specific Instruction-set Processor for Trellis-based Channel Decoding. Ph.D. Thesis, University of Kaiserslautern (2008)Google Scholar
  10. 10.
    Worm, A.: Implementation Issues of Turbo-Decoders. Ph.D. Thesis, University of Kaiserslautern (2001). ISBN 3-925178-72-4Google Scholar
  11. 11.
    Alles, M.: Implementation Aspects of Advanced Channel Decoding. Ph.D. Thesis, University of Kaiserslautern (2010)Google Scholar
  12. 12.
    Hekstra, A.P.: An alternative to metric rescaling in Viterbi decoders. IEEE Trans. Commun. 37(11), 1220–1222 (1989). doi: 10.1109/26.46516 Google Scholar
  13. 13.
    Worm, A., Michel, H., Gilbert, F., Kreiselmaier, G., Thul, M.J., Wehn, N.: Advanced implementation issues of turbo-decoders. In: Proceedings of 2nd International Symposium on Turbo Codes & Related Topics, pp. 351–354, Brest, France (2000)Google Scholar
  14. 14.
    Dielissen, J., Huiskens, J.: State vector reduction for initialization of sliding windows MAP. In: Proceedings of 2nd International Symposium on Turbo Codes & Related Topics, pp. 387–390, Brest, France (2000)Google Scholar
  15. 15.
    Mansour, M.M., Shanbhag, N.R.: VLSI architectures for SISO-APP decoders. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 11(4), 627–650 (2003)Google Scholar
  16. 16.
    Schurgers, C., Engels, M., Catthoor, F.: Energy efficient data transfer and storage organization for a MAP turbo decoder module. In: Proceedings of 1999 International Symposium on Low Power Electronics and Design (ISLPED ’99), pp. 76–81, San Diego, California, USA (1999)Google Scholar
  17. 17.
    Dawid, H., Meyr, H.: Real-time algorithms and VLSI architectures for soft output MAP convolutional decoding. In: Proceedings of 1995 International Symposium on Personal, Indoor, and Mobile Radio Communications (PIMRC ’95), pp. 193–197, Toronto, Canada (1995)Google Scholar
  18. 18.
    Worm, A., Lamm, H., Wehn, N.: VLSI architectures for high-speed MAP decoders. In: Proceedings of Fourteenth International Conference on VLSI Design, pp. 446–453, Bangalore, India (2001)Google Scholar
  19. 19.
    Dawid, H., Gehnen, G., Meyr, H.: MAP channel decoding: algorithm and VLSI architecture. In: VLSI Signal Processing VI, pp. 141–149. IEEE (1993)Google Scholar
  20. 20.
    Fettweis, G., Meyr, H.: High-speed parallel Viterbi decoding: algorithm and VLSI-architecture. IEEE Commun. Mag. 29, 46–55 (1991)CrossRefGoogle Scholar
  21. 21.
    Bickerstaff, M., Davis, L., Thomas, C., Garrett, D., Nicol, C.: A 24 Mb/s radix-4 LogMAP turbo decoder for 3GPP-HSDPA mobile wireless. In: Proceedings of 2003 IEEE International Solid-State Circuits Conference (ISSCC ’03), pp. 150–151, 484, San Francisco, CA, USA (2003)Google Scholar
  22. 22.
    Black, P.J., Meng, T.H.: A 140-Mb/s, 32-state, radix-4 Viterbi decoder. IEEE J. Solid-State Circ. 27(12), 1877–1885 (1992)CrossRefGoogle Scholar
  23. 23.
    Tarable, A., Benedetto, S., Montorsi, G.: Mapping interleaving laws to parallel turbo and LDPC decoder architectures. IEEE Trans. Inf. Theory 50(9), 2002–2009 (2004). doi: 10.1109/TIT.2004.833353 Google Scholar
  24. 24.
    Gilbert, F., Kienle, F., Wehn, N.: Low complexity stopping criteria for UMTS turbo-decoders. In: Proceedings of VTC 2003-Spring. The 57th IEEE Semiannual Vehicular Technology Conference, pp. 2376–2380, Jeju, Korea (2003)Google Scholar
  25. 25.
    May, M., Ilnseher, T., Wehn, N., Raab, W.: A 150 Mbit/s 3GPP LTE turbo code decoder. In: Proceedings of Design, Automation and Test in Europe, 2010 (DATE ’10), pp. 1420–1425 (2010)Google Scholar

Copyright information

© Springer Science+Business Media New York 2014

Authors and Affiliations

  1. 1.Department of Electrical EngineeringTU KaiserslauternKaiserslauternGermany

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