Hardware and VLSI Designs
- 2.7k Downloads
Efficient and secure hardware implementations have become a very popular topic during the last decades. In this chapter, we discuss the fundamental design approaches to successfully implement integrated circuits (ICs) as well as testing methods and optimization techniques to achieve an adequate solution for various application scenarios. A major topic handled in this chapter is security in the context of hardware implementations. We elaborate on the characteristics of modern CMOS circuits with regard to side-channel attacks and we discuss possible countermeasure approaches against such attacks. Furthermore, we describe a comprehensive practical example of combining cryptographic instruction set extensions with hardware countermeasures on a modern 32-bit processor platform. In the last section of this chapter, we argue about the assets and drawbacks of implementing test structures in digital circuits with regard to unintentionally opening security holes as well as about intentionally introducing malicious hardware structures, also called hardware Trojans.
KeywordsVLSI design cycle Design space Advanced encryption standard (AES) Secure hardware design Side-channel analysis Power-analysis attacks Masking Hiding Dual-rail precharge Instruction-set extensions Design for test Hardware Trojans
- 1.Aeroflex Gaisler. The Aeroflex Gaisler Website. http://www.gaisler.com/.
- 2.D. Agrawal, S. Baktir, D. Karakoyunlu, P. Rohatgi, and B. Sunar. Trojan Detection using IC Fingerprinting. In IEEE Symposium on Security and Privacy (SP ’07), Berkeley, Californie, USA, May 20–23 2007, pages 296–310, 2007.Google Scholar
- 3.D. Canright and L. Batina. A Very Compact ”Perfectly Masked” S-Box for AES. In Applied Cryptography and Network Security - ACNS 2008, New York, USA, June 3–6, 2008, Proceedings, volume 5037 of Lecture Notes in Computer Science, pages 446–459. Springer, 2008.Google Scholar
- 4.M. Feldhofer, J. Wolkerstorfer, and V. Rijmen. AES Implementation on a Grain of Sand. IEE Proceedings on Information Security, 152(1):13–20, October 2005.Google Scholar
- 5.Gaisler Research. LEON2 Processor Users Manual. XST Edition. [Online] http://www.gaisler.com/doc/leon2-1.0.30-xst.pdf, July 2005. Version 1.0.30.
- 6.D. Gajski and R. H. Kuhn. New VLSI Tools - Guest Eidtors’ Introduction. IEEE Computer, 16(12):11–14, 1983.Google Scholar
- 7.A. Hodjat and I. Verbauwhede. Interfacing a High Speed Crypto Accelerator to an Embedded CPU. In Conference Record of the Thirty-Eighth Asilomar Conference on Signals, Systems, and Computers, 2004, volume 1, pages 488–492. IEEE, November 2004.Google Scholar
- 8.H. Kaeslin. Digital Integrated Circuit Design - From VLSI Architectures to CMOS Fabrication. Cambridge University Press, 2008. ISBN 978-0-521-88267-5.Google Scholar
- 9.P. C. Kocher. Timing Attacks on Implementations of Diffie-Hellman, RSA, DSS, and Other Systems. In N. Koblitz, editor, Advances in Cryptology - CRYPTO ’96, 16th Annual International Cryptology Conference, Santa Barbara, California, USA, August 18–22, 1996, Proceedings, number 1109 in Lecture Notes in Computer Science, pages 104–113. Springer, 1996.Google Scholar
- 10.P. C. Kocher, J. Jaffe, and B. Jun. Differential Power Analysis. In M. Wiener, editor, Advances in Cryptology - CRYPTO ’99, 19th Annual International Cryptology Conference, Santa Barbara, California, USA, August 15–19, 1999, Proceedings, volume 1666 of Lecture Notes in Computer Science, pages 388–397. Springer, 1999.Google Scholar
- 11.O. Kömmerling and M. G. Kuhn. Design Principles for Tamper-Resistant Smartcard Processors. In Proceedings of the 1st USENIX Workshop on Smartcard Technology (Smartcard ’99), Chicago, Illinois, USA, May 10–11, 1999, pages 9–20, McCormick Place South, May 1999. USENIX Association. ISBN 1-880446-34-0.Google Scholar
- 12.S. Mangard, M. Aigner, and S. Dominikus. A Highly Regular and Scalable AES Hardware Architecture. IEEE Transactions on Computers, 52(4):483–491, April 2003.Google Scholar
- 13.S. Mangard, T. Popp, and B. M. Gammel. Side-Channel Leakage of Masked CMOS Gates. In A. Menezes, editor, Topics in Cryptology - CT-RSA 2005, The Cryptographers’ Track at the RSA Conference 2005, San Francisco, CA, USA, February 14–18, 2005, Proceedings, volume 3376 of Lecture Notes in Computer Science, pages 351–365. Springer, February 2005.Google Scholar
- 14.National Institute of Standards and Technology (NIST). FIPS PUB 140–1: Security Requirements for Cryptographic Modules, 1994. [Online] http://www.itl.nist.gov/fipspubs/.
- 15.National Institute of Standards and Technology (NIST). FIPS-197: Advanced Encryption Standard, November 2001. [Online] http://www.itl.nist.gov/fipspubs/.
- 16.T. Popp, M. Kirschbaum, T. Zefferer, and S. Mangard. Evaluation of the Masked Logic Style MDPL on a Prototype Chip. In P. Paillier and I. Verbauwhede, editors, Cryptographic Hardware and Embedded Systems - CHES 2007, 9th International Workshop, Vienna, Austria, September 10–13, 2007, Proceedings, volume 4727 of Lecture Notes in Computer Science, pages 81–94. Springer, September 2007. ISBN 978-3-540-74734-5.Google Scholar
- 17.T. Popp and S. Mangard. Masked Dual-Rail Pre-Charge Logic: DPA-Resistance without Routing Constraints. In J. R. Rao and B. Sunar, editors, Cryptographic Hardware and Embedded Systems - CHES 2005, 7th International Workshop, Edinburgh, UK, August 29–September 1, 2005, Proceedings, volume 3659 of Lecture Notes in Computer Science, pages 172–186. Springer, 2005.Google Scholar
- 18.J. M. Rabaey. The SPICE Home Page. http://bwrc.eecs.berkeley.edu/Classes/IcBook/SPICE/.
- 19.J. M. Rabaey. Digital Integrated Circuits - A Design Perspective. Electronics and VLSI Series. Prentice Hall, 1st edition, 1996. ISBN 0-13-178609-1.Google Scholar
- 20.P. Schaumont and K. Tiri. Masking and Dual-Rail Logic Dont Add Up. In P. Paillier and I. Verbauwhede, editors, Cryptographic Hardware and Embedded Systems - CHES 2007, 9th International Workshop, Vienna, Austria, September 10–13, 2007, Proceedings, volume 4727 of Lecture Notes in Computer Science, pages 95–106. Springer, September 2007.Google Scholar
- 21.D. Suzuki, M. Saeki, and T. Ichikawa. Random Switching Logic: A New Countermeasure against DPA and Second-Order DPA at the Logic Level. IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E90-A(1):160–168, 2007. ISSN 0916–8508.Google Scholar
- 22.S. Tillich and J. Großschädl. Instruction Set Extensions for Efficient AES Implementation on 32-bit Processors. In L. Goubin and M. Matsui, editors, Cryptographic Hardware and Embedded Systems - CHES 2006, 8th International Workshop, Yokohama, Japan, October 10–13, 2006, Proceedings, volume 4249 of Lecture Notes in Computer Science, pages 270–284. Springer, 2006.Google Scholar
- 23.S. Tillich and J. Großschädl. Power-Analysis Resistant AES Implementation with Instruction Set Extensions. In P. Paillier and I. Verbauwhede, editors, Cryptographic Hardware and Embedded Systems - CHES 2007, 9th International Workshop, Vienna, Austria, September 10–13, 2007, Proceedings, volume 4727 of Lecture Notes in Computer Science, pages 303–319. Springer, September 2007.Google Scholar
- 24.S. Tillich, M. Kirschbaum, and A. Szekely. SCA-Resistant Embedded Processors - The Next Generation. In C. Gates, M. Franz, and J. P. McDermott, editors, 26th Annual Computer Security Applications Conference (ACSAC 2010), 6–10 December 2010, Austin, Texas, USA, pages 211–220. ACM Press, 2010.Google Scholar
- 25.K. Tiri and P. Schaumont. Changing the Odds against Masked Logic. In E. Biham and A. M.Youssef, editors, Selected Areas in Cryptography, 13th International Workshop, SAC 2006, Montreal, Quebec, Canada, August 17–18, 2006, Revised Selected Papers, volume 4356 of Lecture Notes in Computer Science, pp. 134–146. Springer, 2007. [Online] http://rijndael.ece.vt.edu/schaum/papers/2006sac.pdf.
- 26.X. Wang, M. Tehranipoor, and J. Plusquellic. Detecting Malicious Inclusions in Secure Hardware: Challenges and Solutions. In M. Tehranipoor and J. Plusquellic, editors, Hardware-Oriented Security and Trust (HOST 2008), Anaheim, CA, June 9 2008, Proceedings, pages 15–19, 2008.Google Scholar
- 27.N. H. E. Weste and D. Harris. CMOS VLSI Design—A Circuits and Systems Perspective. Addison-Wesley, 3rd edition, May 2004. ISBN 0-321-14901-7.Google Scholar
- 28.F. G. Wolff, C. A. Papachristou, S. Bhunia, and R. S. Chakraborty. Towards Trojan-Free Trusted ICs: Problem Analysis and Detection Scheme. In Design, Automation and Test in Europe (DATE), 10–14 March, 2008, 2008.Google Scholar
- 29.B. Yang, K. Wu, and R. Karri. Scan Based Side Channel Attack on Dedicated Hardware Implementations of Data Encryption Standard. In Proceedings of the International Test Conference on International Test Conference, CCS ’05, pages 139–146, New York, NY, USA, 2005. ACM.Google Scholar
- 30.B. Yang, K. Wu, and R. Karri. Secure Scan: A Design-for-Test Architecture for Crypto Chips. IEEE Trans. on CAD of Integrated Circuits and Systems, 25(10):2287–2293, 2006.Google Scholar
- 31.P. Yu and P. Schaumont. Secure FPGA circuits using controlled placement and routing. In Proceedings of the 5th IEEE/ACM international conference on Hardware/software codesign and system synthesis, Salzburg, Austria, September 30 - October 5, 2007, pages 45–50. ACM Press, September 2007. ISBN 978-1-59593-824-4.Google Scholar