BTI-Induced Statistical Variations



In this section, we discuss the statistics of BTI shift. It is now well known that the BTI mechanism will alter both mean and variance of the threshold voltage VT (as well as that of other device parameters) of a group of MOSFETs under stress. There are two parts—extrinsic and intrinsic—to the induced variations, just as there are to the variations of the unstressed device characteristics. The extrinsic part is key to understanding the variations of BTI-induced shifts of performance (such as FMAX [maximum product clock frequency]) among a population of chips. With deep scaling, the intrinsic contribution to chip-to-chip performance shift variations is increasing. Intrinsic variations will induce device mismatch shift, a potential concern for analog circuits. In addition, it turns out that this random fluctuation component has become extremely important to the problem of random SRAM bit reliability failures due to cell stability degradation.


Compound Poisson Process SRAM Cell Threshold Voltage Shift Equivalent Oxide Thickness Dispersion Factor 
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  1. 1.
    K. Bernstein et al., IBM J. Res. & Dev., v. 50, p. 433 (2006).Google Scholar
  2. 2.
    D. Cochrane and G. Orcutt, J. Amer. Stat. Assoc., v.44, p.32 (1949).Google Scholar
  3. 3.
    C. Blat et al., JAP, v.69, p.1712 (1991).Google Scholar
  4. 4.
    S. Ogawa et al., JAP, v.77, p.1137 (1995).Google Scholar
  5. 5.
    A. Asenov, IEEE TED, v. 45, p.2505 (1998).Google Scholar
  6. 6.
    A. Asenov et al., 2011 Eur. Des. Automation and Test Conf.Google Scholar
  7. 7.
    B. Kaczer et al., IEEE EDL, v.31, p.411 (2010).Google Scholar
  8. 8.
    Y. Chen et al., 2001 IRW Fin. Rep., p.41.Google Scholar
  9. 9.
    R. Thewes et al., IEEE TED, v.45, p 2505 (1998).Google Scholar
  10. 10.
    C. Schlünder et al., Microelec. Rel., v.45, p.39 (2005).Google Scholar
  11. 11.
    S. Rauch, IEEE TDMR, v.2, p. 89 (2002).Google Scholar
  12. 12.
    M. Agostinelli et al., Microelec. Rel., v.46, p.63 (2005).Google Scholar
  13. 13.
    G. La Rosa et al., Proc. 2006 IRPS, p.274.Google Scholar
  14. 14.
    A. Haggag et al, Proc. 2007 IRPS, p.452.Google Scholar
  15. 15.
    S. Rauch, IEEE TDMR, v.7, p.524 (2007).Google Scholar
  16. 16.
    M. Alam and S. Mahapatra, Microelec. Rel., v.45, p.71 (2005).Google Scholar
  17. 17.
    H. Reisinger et al., Proc. 2006 IRPS, p.448.Google Scholar
  18. 18.
    M. Agostinelli et al., Proc. 2005 IRPS, p.529.Google Scholar
  19. 19.
    B. Bindu et al., 2009 IIRW Final Report, p.94.Google Scholar
  20. 20.
    K. Takeuchi, 1998 Symp. VLSI Tech. Dig., p.72.Google Scholar
  21. 21.
    D. Snyder, Random Point Processes, Wiley (1975).Google Scholar
  22. 22.
    J. Skellam, J. Royal Stat. Soc., Series A, v.109, p. 296 (1946).Google Scholar
  23. 23.
    T. Grasser et al., IEEE TED, v. 58, p.3652 (2011).Google Scholar
  24. 24.
    T. Grasser et al., 2009 IEDM, p.729.Google Scholar
  25. 25.
    V. Huard et al., 2005 Proc. IIRW, p.5.Google Scholar
  26. 26.
    A. Ghetti et al., Proc. 2008 IRPS, p.610.Google Scholar
  27. 27.
    A. Ghetti et al., IEEE TED, v.56, p.1746 (2009).Google Scholar
  28. 28.
    J. Franco, 2012 IRPS, p.5A.4.1.Google Scholar
  29. 29.
    B. Kaczer et al., Proc. 2010 IRPS, p.26.Google Scholar
  30. 30.
    H. Alexandersson, J. Climate and Appl. Meteor., v.24, p.1285 (1985).Google Scholar
  31. 31.
    M. Toledano-Luque et al., 2011 VLSI Symp. Dig., pp 152.Google Scholar
  32. 32.
    V. Huard et al., Proc. 2008 IRPS, p.289.Google Scholar
  33. 33.
    M. Bukhori et al., 2010 IIRW Fin Rep., p76.Google Scholar
  34. 34.
    T. Grasser et al., Proc. 2010 IRPS, p.16.Google Scholar
  35. 35.
    T. Fischer et al., 2008 Eur. Sol.-St. Dev. Res. Conf., p.51.Google Scholar
  36. 36.
    K. Ohmori et al., 2008 IEDM Dig., p.409.Google Scholar
  37. 37.
    H. Dadgour et al., IEEE TED, v.57, p.2504 (2010).Google Scholar
  38. 38.
    S. Markov et al., 2011 IEEE Int. SOI Conf., p. 3.2.Google Scholar
  39. 39.
    X. Wang et al., 2012 IEEE SISPAD, p.256.Google Scholar
  40. 40.
    S. Rasouli et al., 2010 IEEE/ACM ICCAD, p.714.Google Scholar
  41. 41.
    C. Young et al., IEEE TED, v.56, p.1322 (2009).Google Scholar
  42. 42.
    S.M. Amoroso, L. Gerrer, F. Adamu-Lema, S. Markov, A. Asenov, in Statistical Study of Bias Temperature Instabilities by Means of 3D ‘Atomistic’ Simulation, ed. by T. Grasser. Bias Temperature Instability for Devices and Circuits (Springer, New York, 2013)Google Scholar
  43. 43.
    J. Martin-Martinez, R. Rodriguez, M. Nafria, Simulation of BTI Related Time-Dependent Variability in CMOS Circuits, ed. by T. Grasser. Bias Temperature Instability for Devices and Circuits. (Springer, New York, 2013)Google Scholar
  44. 44.
    H. Reisinger, The Time Dependent Defect Spectroscopy, ed. by T. Grasser. Bias Temperature Instability for Devices and Circuits (Springer, New York, 2013)Google Scholar

Copyright information

© Springer Science+Business Media New York 2014

Authors and Affiliations

  1. 1.IBM MicroelectronicsHopewell Jct.USA

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