Characterization of Individual Traps in High-κ Oxides

Abstract

As the result of the vertical scaling of the CMOS technology, high-κ materials were introduced in the gate stack in order to reduce leakage current while keeping electrostatic control over the channel. Despite the high level of the bulk defects of these materials, only a handful of defects are present in the gate oxide due to the reduced lateral dimensions of the current CMOS technology. However, the relative impact of these traps on the device characteristics increases. In Chap. 17, it has been demonstrated for the conventional SiO₂/poly-Si stack that the properties of each Si/SiO₂ defect, such as its capture and emission times and its impact, are voltage and/or temperature dependent and widely distributed. In this chapter, we show that identical properties are followed by high-κ-based dielectrics. The stochastical nature of the behavior of the dielectric traps results in each of the nominally identical nm-scaled devices behaving very differently during operation and, therefore, increasing time-dependent variability (heteroskedasticity). Consequently, the lifetime of nm-sized high-κ devices cannot be predicted individually, but can be only described in terms of time (or workload)-dependent distributions.