Abstract
This chapter presents a comprehensive simulation study of the reliability performance in contemporary bulk MOSFET devices. With the CMOS technology entering in the nanoscale era, the statistical variability due to random dopant fluctuations plays a critical role in determining the transistor reliability performance. As a consequence, in contemporary devices, reliability and variability cannot be considered anymore as separate concepts. The reliability has to be reinterpreted as a time-dependent form of variability. In the first part of this chapter we introduce computational models and methods for modelling the reliability phenomena in presence of statistical variability. In particular we present both a frozen-time and a dynamical approach, showing details of their implementation and verification. In the second part of the chapter we report a broad set of simulation results highlighting the importance of variability in reliability evaluation of nanoscale devices. In particular we analyse the impact of variability on the single transistor and on many different transistors in presence of a single trapped charge. Then we show the effects related to multiple trapped charges. Finally the statistical results obtained using the frozen-time and the dynamical methods are compared in terms of accuracy in predicting the statistical dispersion in threshold voltage shifts.
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Acknowledgements
The results presented here have been obtained through extensive research activity funded by the European Community through the FP7 project “MORDRED” no. 261868.
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Amoroso, S.M., Gerrer, L., Adamu-Lema, F., Markov, S., Asenov, A. (2014). Statistical Study of Bias Temperature Instabilities by Means of 3D “Atomistic” Simulation. In: Grasser, T. (eds) Bias Temperature Instability for Devices and Circuits. Springer, New York, NY. https://doi.org/10.1007/978-1-4614-7909-3_13
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