Advertisement

Motivation for a Memory-Based Computing Hardware

  • Somnath Paul
  • Swarup Bhunia
Chapter
  • 763 Downloads

Abstract

In this chapter we first provide a summary of the desired characteristics that a compute framework must have to overcome the challenges faced by conventional hardware and software reconfigurable frameworks at nanoscale technologies. We then provide an outline for a new computing model which bridges the gap between memory and logic. Given the rapid evolution of CMOS and non-CMOS memory technologies, we explain the benefits of such in-memory computing model.

Keywords

Graphical Processing Unit Memory Technology Dynamic Random Access Memory Memory Array Static Random Access Memory 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

References

  1. 1.
    J.L. Gustafson, “Reevaluating Amdahl’s Law”. ACM Comm. 31(5), 532–533 (1988)CrossRefGoogle Scholar
  2. 2.
  3. 3.
    “Assessment of the Potential & Maturity of Selected Emerging Research Memory Technologies” http://www.itrs.net/links/2010itrs/2010Update/ToPost/ERD_ERM_2010FINALReportMemoryAssessment_ITRS.pdf
  4. 4.
    H. Singh, M. Lee, G. Lu, F.J. Kurdahi, N. Bagherzadeh, E.M. Chaves Filho, “MorphoSys: an integrated reconfigurable system for data-parallel and computation-intensive applications”. IEEE Trans. Comput. 49(5), 465–481 (2000)CrossRefGoogle Scholar
  5. 5.
    S.C. Goldstein, H. Schmit, M. Moe, M. Budiu, S. Cadambi, R.R. Taylor, R. Laufer, “PipeRench: A Coprocessor for Streaming Multimedia Acceleration”, in Intl. Symp. on Computer Architecture, 1999Google Scholar
  6. 6.
    S. Yehia, N. Clark, S.A. Mahlke, K. Flautner, “Exploring the Design Space of LUTbased Transparent Accelerators”, in CASES, 2005Google Scholar
  7. 7.
    A. Agarwal et al., “A 320mV-to-1.2V On-Die Fine-Grained Reconfigurable Fabric for DSP/Media Accelerators in 32nm CMOS”, in Intl. Solid-State Circuits Conference, 2010Google Scholar
  8. 8.
    [Online], “The Landscape of Parallel Computing Research: A View From Berkeley”. http://view.eecs.berkeley.edu/wiki/Main_Page
  9. 9.
    [Online], “ITRS 2007: Interconnect”. http://www.itrs.net/links/2007itrs/home2007.htm
  10. 10.
    T.W. Andre et al., “A 4-Mb 0.18-m 1T1MTJ Toggle MRAM with Balanced Three Input Sensing Scheme and Locally Mirrored Unidirectional Write Drivers”, in Intl. Solid-State Circuits Conference, 2004Google Scholar
  11. 11.
    W.Y. Cho et al., “A 0.18-m 3.0-V 64-Mb nonvolatile phase-transition random access memory (PRAM)”. IEEE J. Solid State Circ. 40, 293–300 (2005)Google Scholar
  12. 12.
    S.T. Hsu, T. Li, N. Awaya, “Resistance random access memory switching mechanism”. Appl. Phys., 024517–024517-8 (2007)Google Scholar
  13. 13.
    T. Rueckes et al., “Carbon nanotube-based nonvolatile random access memory for molecular computing” Science. 289(5476), 94–97 (2000)CrossRefGoogle Scholar
  14. 14.
    W. Wu et al., “One-kilobit cross-bar molecular memory circuits at 30-nm half-pitch fabricated by nanoimprint lithography”. Appl. Phys., 1173–1178 (2005)Google Scholar
  15. 15.
    S. Paul, S. Bhunia, “Computing with Nanoscale Memory: Model and Architecture”, in Intl. Symp on Nanoscale Architecture, 2011Google Scholar
  16. 16.
    M.R. Stan et al., “Molecular electronics: from devices and interconnect to circuits and architecture”. Proc. IEEE 91, 1947–1957 (2003)Google Scholar
  17. 17.
    S. Mukhopadhyay, H. Mahmoodi, K. Roy, “Modeling of failure probability and statistical design of SRAM array for yield enhancement in nanoscaled CMOS”. IEEE Trans. Comput. Aided Des. Integrat. Circ. Syst. 24(12), 1859–1880 (2005)CrossRefGoogle Scholar

Copyright information

© Springer Science+Business Media New York 2014

Authors and Affiliations

  • Somnath Paul
    • 1
  • Swarup Bhunia
    • 2
  1. 1.Intel LabsHillsboroUSA
  2. 2.Department of EECSCase Western Reserve UniversityClevelandUSA

Personalised recommendations