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Summary

  • Somnath Paul
  • Swarup Bhunia
Chapter
  • 725 Downloads

Abstract

We have presented a novel hardware reconfigurable framework that utilizes two-dimensional memory array for reconfigurable computing. The idea proposed is to partition an application to multi-input multi-output LUTs and map them to dense memory arrays at each compute element of the framework. Each of these compute elements evaluates the LUTs over multiple clock cycles in a temporal manner and multiple compute elements combine to spatially map any large application.

Keywords

Reconfigurable Computing Memory Array Multiple Clock Cycles Temporal Manner Application Mapping Process 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

Copyright information

© Springer Science+Business Media New York 2014

Authors and Affiliations

  • Somnath Paul
    • 1
  • Swarup Bhunia
    • 2
  1. 1.Intel LabsHillsboroUSA
  2. 2.Department of EECSCase Western Reserve UniversityClevelandUSA

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